Electrical Engineering Department
Spring 2010
EE115C – Digital Electronic Circuits Homework #3 Due Thursday, April 22, 6pm @ 56-147E EIV
Solution
Problem 1 – VTC and Inverter Analysis Figure 1a shows a standard CMOS inverter. However, during the process of manufacturing, the
circuit was contaminated with a particle and the gate of the PMOS transistor got shorted to GND
instead of being connected to the input. The contaminated inverter circuit could be modeled as
shown in Figure 1b.
Figure 1: CMOS Inverter.
(Note: L indicates drawn channel length, assume xd = 15nm).
1A
Find VOH, VOL, and VM for the inverters in Figures 1a and 1b.
Sol:
The circuit in Figure 1a:
Regular CMOS inverter
Æ
VOH =1.0V
VOL=0V
Little thinking experiment to validate this:
Since we don’t know VOH and VOL, let’s start from VOH(1) somewhere above VM and
calculate corresponding VOL(1). Pick another point for VOH(2) > VOH(1), you will find
VOH(2) < VOL(1). Keep iterating until you hit bounds: VOH = VDD, VOL = 0.
For VM (which we expect to be around VDD/2 = 0.5V), we can assume that both
transistors are in saturation since VDSAT,N = 0.3V > VGT,N; |VDSAT,P|=0.4V > |VGT,P|
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I dN =
Spring 2010
1 ' WN
kN
(VGSN − VTHN ) 2 (1 + λ NVDSN )
2
LN
= 0.5 × 130 × 5.64 × (VM − 0.17) 2 (1 + 0.75 ×VM )
| I dP |=
1 ' WP
| kP |
(VGSP − VTHP ) 2 (1 + λ PVDSP )
LP
2
= 0.5 × 100 × 2.82 × (1 − VM − 0.2) 2 (1 + 0.62 × (1 − VM ))
Set IdN = IdP and solve for VM
Æ
VM = 0.409 V
The circuit in Figure 1b:
First iteration:
(1)
Vin = VOH =1V Æ Calculate Vout (Vin =VOH = 1V)
Assuming VOL < VDSAT, NMOS is in linear mode, PMOS is in vel-satutration
Result: Vout = VOL(1) = 0.119V
Validate assumptions:
NMOS: VDSN = 0.119V < VDSATN = 0.3V < VGTN = 0.83V
PMOS: |VDSATP| = 0.4V < |VGTP| = 0.8V < |VDSP| = 0.881V
(linear)
(vel-sat)
The value of VOL obtained here satisfies the assumption that NMOS is OFF when VOL is
applied. Therefore: VOH = 1V
VOL = 0.12V
For VM, we can assume PMOS in linear, and NMOS in vel-sat regime
V2
WN
I dN = k N'
((VGSN − VTHN )VDSAT − DSAT )(1 + λ NVDSN )
LN
2
= 130 × 5.64 × ((VM − 0.17) × 0.3 − 0.045)(1 + 0.75 ×VM )
| I dP |=| k 'p |
V2
WP
((VGSP − VTHP )VDSP − DSP )(1 + λ PVDSP )
LP
2
= 100 × 2.82 × (1 − VM ) × ((1 − 0.2) − 0.5 × (1 − VM ))(1 + 0.62 × (1 − VM ))
Set IdN = |IdP| and solve for VM:
VM = 0.604V
1B
Use SPECTRE to plot the VTC curves of the two inverters. Plot both VTCs and also the
45o line (Vin = Vout) all on one graph. Compare and discuss the differences in the VTC
curves, robustness, and regeneration (assuming the output will connect to another inverter
of the same kind) of these two inverters.
Electrical Engineering Department
Spring 2010
Use following parameters for hand calculations:
VDD = 1.0V, VM = 0.5V, VDSAT = 0.3V for NMOS, and VDSAT = −0.4V for PMOS
NMOS: VT0 = 0.17V, kn’ = 130μA/V2, γ = 0.1V1/2, λ = 0.75V-1, 2ΦF = 0.6V
PMOS: VT0 = −0.20V, kp’= −100μA/V2, γ= −0.16V1/2, λ= −0.62V-1 2ΦF = −0.6V
Sol:
Spectre simulation results are shown below:
1
Figure 2-2
Pseudo NMOS
Inverter
0.9
0.8
VOUT volt
0.7
Figure 2-1
CMOS inverter
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VIN volt
0.7
0.8
0.9
1
Note: because the simulations are based on quite complex models, you may find a mismatch
between the simulation results and simplified hand-calculation from 2A. This is normal.
Differences (simulation vs. hand-calculations):
VTC curves: VOL for the circuit in Fig. 2-2 is not zero, and the curve is shifted to the
right from the curve of the CMOS inverter. This is because the PMOS is
always turned on (recall the discussion in class about increased size of the
PMOS transistor)
Robustness:
NML (Fig. 2-2) is smaller, hence the circuit in Fig. 1b is less robust
NML (Fig. 2-2) = 0.27V(VIL)-0.07V(VOL) = 0.20V
NML (Fig. 2-1) = 0.26V(VIL)-0.00V(VOL) = 0.26V
In both circuits, NMH is greater than NML
Note: VIL values are estimated graphically.
Regeneration: both circuits are good, because the absolute value of the gain in the
transition region (slope of the VTC curve) is greater than 1. However, the
circuit in Fig. 1a regenerates faster due to a larger gain.
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Spring 2010
Problem 2 – Equivalent Resistance Consider NMOS device with W = 240nm and L = 100nm (effective L = 70nm). Using the
resistor averaging technique discussed in class, Equations (3.42) and (3.43) from textbook, and
parameters from Hw-2 / Prob-1, calculate Ron as VDD changes from 0.4V-1V in steps of 0.2V.
Compare the results of your hand calculations with simulation results. Assume VDSATn = 0.3V.
Sol: We have the following from textbook equations and HW2:
λ = 0.795V −1
k ' = 129.5μ A / V 2
Leff = 70nm
Vth = 0.168V
Vdsatn = 0.3V
W
((Vdd − Vth ) *Vdsat − Vdsat 2 / 2)
L
3 Vdd
5
Ron _ approx =
(1 − λVdd )
4 I dsat
6
I dsat = k '
Ron _ exact =
3 Vdd
7
(1 − λVdd )
4 I dsat
9
Using the above data we get the following results. For Ron_simulated we have two cases, with an
average of two data point (VDD, VDD/2) and an average over the entire range VDD – VDD/2.
VDD [V]
0.4
0.6
0.8
1.0
IDSAT (μA)
RON_APPROX
(KΩ)
RON_EXACT
(KΩ)
RON_SIM(2points)
(KΩ)
RON_SIM(range)
(KΩ)
7.05
31.65
33.69
8.24
60.33
4.87
86.97
3.12
32.38
8.58
5.21
3.49
27.79
9
6.51
5
25.34
9.09
6.48
4.9
Discussion:
The above solution approximates λ as a single value. From home work 2, we know that λ varies
significantly with VGS. In digital circuits, VGS is often equal to VDD. Thus we need to consider
different values of λ for calculation of RON for different supply voltages.
VGS [V]
λ [1/V]
0.4
5.53
0.6
1.19
0.8
0.757
1.0
0.67
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Spring 2010
(Note: Value for VGS = 0.6 and 0.8 V are updates from simulations. These were not present in
solution to Q.1C Home work 2) Let us look at the results with these refined values of λ
VGS [V]
RON APPROX
RON EXACT
RON SIM(2points)
RON SIM(range)
0.4
-35.83
-30.06
27.79 K
25.34
0.6
5.4
5.94
9
9.09
0.8
4.925
5.26
6.51
6.48
1.0
3.8
4.12
5
4.9
RON is negative for 0.4V and significantly under estimates the delay at 0.6V! Did we not expect
to get a better match with the new values λ? Here is the catch:
The formulae used for calculation of RON (approximate and exact), assume that the transistor is
in velocity saturated mode of operation for the entire range VDD to VDD/2. While this assumption
is true for 0.8V and 1V, it is not valid at 0.6 V and 0.4 V. Hence we see that the model does not
give reasonable values for RON at 0.4 and 0.6 V. On the other hand, the results of the model and
simulations are comparable for 0.8 V and 1 V supplies.
Problem 3 – Inverter in Subthreshold The inverter below, operates with VDD=0.15 V and is composed of Vtn=|Vtp| = 0.20 V devices.
The devices have identical I0 and n but the channel modulation constants are different
(λn = 0.75V-1, λp = -0.62V-1, n = 1.5 and kT/q = 26 mV).
a) Calculate the switching threshold (VM) of this inverter.
Sol:
Both devices are in the subthreshold region (VDD < VT)
I DN = I DP
I 0e
I 0e
VGSN
n ( kT / q )
VM
n ( kT / q )
(1 − e
(1 − e
−
−
VDSN
( kT / q )
VM
( kT / q )
)(1 + λ NVDSN ) = I 0e
)(1 + λ NVM ) = I 0 e
VGSP
n ( kT / q )
0.15 −VM
n ( kT / q )
(1 − e
(1 − e
−
−
VDSP
( kT / q )
0.15 −VM
( kT / q )
)(1 + λ PVDSP )
)(1 + λ P (0.15 − VM )
We can solve the above equation for VM using a math solver. You can take the following
approach: plot IDN and IDP and as function of VM and find out the intersection point of
these two curves – this value corresponds to VM.
VM = 0.075 V
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b) Calculate VIL and VIH of the inverter.
(hint: equation 5.12 in textbook )
0.15V
0.4V
Vin
Vout
Figure 3
Hint: Use the subthreshold voltage-current relation.
Sol:
VIH = VM – VM/g
VIL = VM + (VDD–VM)/g
⎞
⎛ 1 ⎞ ⎛ VDD
From equation 5.12: g = − ⎜ ⎟ ⎜ e 2φT − 1⎟ = –11.26
⎝ n ⎠⎝
⎠
VIH = 0.075 – 0.075/(–11.26) = 0.082V, VIL = VM + (VDD–VM)/g = 0.068V
VIH = 0.082 V
VIL =0.068 V
Spring 2010