Iwai lab. Team III-V
Effect of pretreatment for high-k/InGaAs interface property
○ Hiroshi
Oomine1, Dariush H. Zadeh1, Kuniyuki Kakushima2Akira Nishiyama2, Nobuyuki Sugii2,
Yoshinori Kataoka2, Hitoshi Wakabayashi2, Kazuo Tsutsui2, Kenji Natori1, and Hiroshi Iwai1
Tokyo Tech. FRC1, Tokyo Tech. IGSSE2 E-mail: [email protected]
Background
3D
Bulk Planar
LSIの消費電力
Low power consumption of LSI
P = αNCfVdd2+NIoffVdd
Vdd: Supply voltage
Si
In0.53Ga0.47As
f : Active frequency
Electron
7800
Ioff: leakage current at off
600
mobility(cm2/Vs)
C : capacitance
N : Number of transistor Ref: intel HP
Importance of pre-treatment
Cleaning methods
decided interface
and electrical
properties.
PMA dependence
CET (nm)
10% hydrochloric oncentration
can be obtain good CV curve.
HCl cleaning can be reduce
CET value at under 400oC PMA
E-Ei = 0.1 eV
Dit (eV/cm)
High ON current at low supply
voltage
4
3.5
3
2.5
1.00E+14
2
1014
Dit value is reduced HCl (10%),
however HF (20%) cleaning is
more low Dit value.
1.00E+13
1.00E+12
270
1.00E+01
1.00E+00
1.0
Jg at 1V (A/cm2)
14nm, 11nm, 8nm, 5nm, 3nm…
MG/HK 32nm 22nm Performance improvement by scaling
45nm
is difficult.
High mobility channel material
65nm
1.00E-01
1.00E-02-2
10
370
470
PMA temperature (oC)
570
Treatment.
HCl (7%)
HCl (10%)
1.00E-03
HCl (36%)
1.00E-04
10-4
HF (20%)
Jg is almost unchanged with HF
acid and HCl acid.
This result indicated that Jg is
determined Al2O3 film quality.
1.00E-05
1.00E-06
10-6
1.00E-07
1.00E-08
10-8
270
370
470
570
PMA temperature (oC)
Acetone-ethanol degreasing
Native oxide removal (HCｌ 7~36% HF 20%)
(NH4)2S surface treatment
1 Cycle
ALD-La2O3 deposition (10 nm)
Gate metal (TiN/W) deposition
by RF sputteing
Supply Gas:
H2O
Ar Purge
S: 1×1016
n-InGaAs
n-InGaAs
n-InGaAs
n-InP
n-InP
n-InP
Dit (eV/cm)
Effect of cleaning method
0.6
0.4
0.2
CET=
2.6nm
5 kHz
10 kHz
100 kHz
1 MHz
Capacitance (μF/cm2)
Capacitance (μF/cm2)
0.8
320oC
0
-1.5 -1 -0.5 0 0.5 1 1.5
Gate Voltage (V)
1.2
1
0.8
0.6
PMA
HF(20%) only
320oC
HCl (10%)+(NH4)2S
CET=
2.7nm
1012
270
PMA 320oC
HF(20%) only
0.8
0.6
0.4
0.2
CET=
2.9nm
0
E-Ei = 0.1 eV
n-In0.53Ga0.47As
Results and Discussion
1.0
0.2
CET=
3.1nm
1013
TiN 45 nm
W 5 nm
Al
HCl (7%)+(NH4)2S
5 kHz
10 kHz
100 kHz
1 MHz
-1.5 -1 -0.5 0 0.5 1 1.5
Gate Voltage (V)
n+-InP
FGA
0.4
La22O33(10
nm)
Al
(7nm)
Measurements
1.2
0.6
HF(20%)+
S-passivation
0
n-InGaAs
n-InP
Gate pattern by ICPRIE
PMA (3% H2) for 5 min
Backside Al contact
Ar Purge
Supply Gas:
TMA
0.8
1
Capacitance (mF/cm2)
Experimental Procedure
Capacitance (μF/cm2)
Effect of S-passivation
PMA 320oC
1
HF(20%)+
S-passivation
-1.5 -1 -0.5 0 0.5 1 1.5
Gate Voltage (V)
Both sample (with or without Spassivation) shows superior CV
response with significant
reduction in stretch-out in enter
voltage sweep range.
With or without S-passivation
ALD deposited Al2O3 shows
almost same Dit values
370
470
570
o
PMA temperature. ( C)
Conclusions
0.4
HCl (10%) cleaning methods is effectiveness for the low Dit value.
0.2
Gate leakage current Jg is not affect by cleaning methods HCl or
HF acid for native oxide remove.
In ALD deposition methods, Dit values don’t change significantly
regardless of S-passivation.
0
-1.5 -1 -0.5 0 0.5 1 1.5
Gate Voltage (V)