Nihaar N. Mahatme
2000 Grand Ave. Apt 309
Nashville TN 37212.
[email protected]
615-473-2671
OBJECTIVE: Seeking full-time positions to pursue cutting-edge research in the area of low-power, reliable devices and circuits
RESEARCH INTERESTS: Circuit reliability, soft error resilience, low-power design for medical and sensor applications
EDUCATION:
 Ph.D (Electrical Engineering), Vanderbilt University
GPA : 3.97/4.0
Expected : Spring 2014
Doctoral Advisors : Dr. Bharat Bhuva
Dr. Ronald Schrimpf
 MS (Electrical Engineering), Vanderbilt University
November 2011
 Bachelor of Electrical Engineering, University of Mumbai, May 2009
RESEARCH HIGHLIGHTS
I. DOCTORAL RESEARCH: Design of Reliability-Aware Low Power Circuits
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My research involves developing low power design strategies for soft-error mitigation
Soft errors are transient errors that occur due to radiation strikes on electronic circuits.
Experimentally proved that impact of soft errors in logic circuits will increase with scaling
Designed soft error resilient circuits that also reduce power consumption
Successful tape-outs and radiation testing of designs on 40 nm, 28 nm and 20 nm technologies across multiple foundries
Published multiple papers in the area of nuclear and space radiation effects including best paper awards
Core Competencies : Low-power circuit design, soft-error reliability, device physics
II. INTERNSHIPS:
Ultra Low-Power Design for
Reliability
FreeScale Semiconductor, Austin
Summer 2013
Advisor: Dr. Glenn Abeln
 Currently optimizing SRAM designs to minimize leakage
 Exploring techniques to reliably operate SRAMs at extreme
temperatures (~ 165 C) for automotive applications
Technology Experience
28 nm GlobalFoundries
28 nm TSMC
Low-Power Design for Reliability
CISCO Systems Inc.,
Summer 2012
Advisor: Dr. Shi-Jie Wen
 Designed low-power soft-error reliability-aware circuits
 Used techniques like parallel processing, circuit partition and
pre-computation to reduce dynamic power consumption and
increase reliability
 Successful tape-out of 3 ICs
Tape-outs :
28 nm ST Micro ULP,
40 nm UMC Bulk CMOS
Softwares: Cadence
Design Suite
Radiation Effects on 1-T DRAMs
(Memories)
IMEC, Belgium,
Summer 2011
(In collaboration with Micron
technologies)
Advisor: Dr. Guido Groeseneken
 Full characterization of UltraThin body FDSOI devices
 Reliability assessment (endurance) of 1-T DRAM memories
 Quantified the impact of interface-traps on memory retention
time and programming window
 Evaluated the robustness of DRAMs under radiation stress for
high-reliability space applications
 Statistically modeling of DRAM retention time
Technology experience :
Imec Low-Power UltraThin body and BOX
FDSOI
Softwares: MATLAB, Perl
45-nm Strained Silicon SRAM
Reliability
Taiwan Semiconductor
Manufacturing Company, Taiwan
Summer 2010
Advisor : Dr. Anthony Oates
 Analyzed the impact of strain on the device characteristics
 3-D TCAD modeling for dual and triple well processes
 Developed novel layout techniques that use strain to reduce the
soft-error rate
Technology experience :
45 nm dual and triple-well
bulk TSMC
Softwares: Sentaurus
TCAD, SPICE
Non-invasive measurement of
Electrogastrography(abdominal)
signals
2008-09, BARC, India
 Developed non-invasive techniques to measure the frequency of
electrogastrographic (abdominal) signals
 Statistical deviation in frequency of signals can be used to
identify abdominal disorders like ulcers and cancers
Softwares: Ultrasim,
MATLAB
III. PUBLICATIONS (JOURNAL)
 N. N. Mahatme et al., “Experimental Estimation of the Window of Vulnerability for Logic Circuits”, IEEE Transactions on
Nuclear Science, (accepted : IEEE Transactions on Nuclear Science).
 N. N. Mahatme et al., “An efficient technique to select logic nodes for single event transient pulse-width reduction”,
Microelectronics Reliability, Volume: 53, Issue: 1, Page (s) 114–117, 2013.
 D. B. Limbrick, N. N. Mahatme, W. H. Robinson, B. L. Bhuva, “Determining the efficacy Selective Node Hardening
Techniques using Standard Cells, IEEE Transactions on Nuclear Science, (accepted, 2013).
 N. N. Mahatme et al., “Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor
Floating Body RAMs”, IEEE Transactions on Nuclear Science, Volume: 59, Issue: 6, Part: 1; Page(s): 2966 – 2973, 2012.
Outstanding Paper Award at IEEE Nuclear and Space Radiation Effects Conference, 2012
 N. N. Mahatme et al., “Impact of Strained-Si PMOS Transistors on SRAM Soft Error Rates”, IEEE Transactions on Nuclear
Science, Volume:59, Issue: 4 , Part: 1, Page(s): 845 – 850, 2012.
 S. Jagannathan, T. D. Loveless, B. L. Bhuva, N. J. Gaspard, N. N. Mahatme, T. Assis, S. J. Wen, R. Wong, L. W. Massengill,
“Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology Nuclear
Science”, IEEE Transactions on Nuclear Science, Volume:59 , Issue: 6 , Part: 1, Page(s): 2796 – 2802, 2012.
 N. N. Mahatme et al., “Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process, IEEE
Transactions on Nuclear Science, Volume:58, Issue: 6 , Part: 1, Publication Year: 2011 , Page(s): 2719 - 2725, 2011.
 I. Chatterjee, B. Narasimham, N. N. Mahatme, B. L. Bhuva, R. D. Schrimpf, J. K. Wang, B. Bartz, E. Pitta, M. Buer, “SingleEvent Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs”, IEEE Transactions on Nuclear
Science, Volume: 58, Issue: 6, Part: 1, Page(s): 2761 – 2767, 2011.
 N. N. Mahatme et al., "Geometry Dependence of Reverse Narrow Channel Effects in Fully Depleted SOI devices with
UltraThin Buried Oxide and Body", IEEE Transactions on Device Materials and Reliability (under review).
CONFERENCE
 N. N. Mahatme et al., “Estimating the Frequency Threshold for Logic Soft Errors”, IEEE International Reliability Physics
Symposium, 2013 (to appear).
 N. N. Mahatme et al., “Total ionizing dose effects on ultra thin buried oxide floating body memories”, IEEE International
Reliability Physics Symposium, Page(s): MY.3.1- MY.3.5, 2012.
 M. Aoulaiche, N. Collaert, P. Blomme, E. Simoen, L. Altimime, G. Groeseneken, M. Jurczak, L. Mendes Almeida, C. Caillat,
N. N. Mahatme, “Effect of interface states on 1T-FBRAM cell retention”, IEEE International Reliability Physics Symposium,
Page(s): MY.1.1- MY.1.4, 2012.
 C. Claeys, M. Aoulaiche, E. Simoen, A. Griffoni, D. Kobayashi, N. N. Mahatme, R. A. Reed, R. D. Schrimpf, P. G. D.
Agopian, J. A. Martino, “Radiation hardness aspects of advanced FinFET and UTBOX devices”, IEEE SOI Conference, Page(s):
1 – 2, 2012.
 N. N. Mahatme et al., “Analysis os Multiple Cell Upsets due to neutrons in SRAMs for Deep-N-Well process”, IEEE
International Reliability Physics Symposium, pp 1031-1035, 2011.
 S. Jagannathan, Z. Diggins, N. N. Mahatme, T. D. Loveless, B. L. Bhuva, S.-J. Wen, R. Wong, L. W. Massengill, “Temperature
dependence of soft error rate in flip-flop designs”, IEEE International Reliability Physics Symposium, Page(s): SE.2.1 - SE.2.6,
2011.
 N. N. Mahatme et al., “Impact of strained-Si PMOS transistors on SRAM soft error rates”, Radiation and Its Effects on
Components and Systems Conference (RADECS), Page(s): 202 – 206, 2011.
 N. N. Mahatme et al., “Analysis of soft error rates in combinational and sequential logic and implications of hardening for
advanced technologies”, IEEE International Reliability Physics Symposium, Page(s): 1031 – 1035, 2010.
HONORS AND AWARDS:
 IEEE Nuclear and Plasma Society Paul Phelps Award, 2012
 Outstanding Student Paper Award, NSREC 2012
 K.C. Mahindra Scholarship for International Studies, 2009
SERVICE:
 Working with professors to write proposals to NSF, Army Research Office, NASA & LosAlamos National Labs
 Peer reviewer for IEEE TDMR, Microelectronics Reliability Journal
 Teaching assistant for VLSI Design, Digital Design and Electrical Networks courses
EXPERIMENTAL SKILLS:
 Device-level characterization of CMOS bulk and SOI devices under various stress conditions
 Alpha particle, X-ray, neutron and heavy-ion radiation exposure and test of devices and circuits
SOFTWARE SKILLS: CADENCE Design Suite, Sentaurus TCAD, Synopsys Design Compiler, MATLAB, C, Perl