CMPT-150
Introduction to Computer Design
SFU, Harbour Centre, Spring 2007
Lecture 16: Mar. 6, 2007
• Memory Basics
– Random Access Memory (RAM)
• Computer Design Basics
– General Purpose Computer
– Instruction Set Architecture
Memory Definitions
• Memory: A collection of storage cells together with the
necessary circuits to transfer information to and from them.
• Memory Data: a bit or a collection of bits to be stored into or
accessed from memory cells.
• Typical data elements:
– Bit: a single binary digit.
– Byte: a collection of 8 bits.
– Word: a collection of bits that is the a typical unit of
access for the memory. Usually a power of two multiple of
bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)
– Datapath
Memory Definitions (cont’)
Example
• Memory size is measured by the number of bytes or words.
• 1K x 16 RAM: 1K words,
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–
–
–
Kilo (Kb):
Megabyte (Mb):
Gigabyte (Gb):
Terabyte (Tb):
1024 bytes = 210 bytes
1024 Kilobyte = 220 bytes
1024 Megabyte = 230 bytes
1024 Gigabyte = 240 bytes
• Memory Organization: Usually organized as an indexed array
of words. Index = Address.
• Memory Operations: operations on memory data supported by
the memory unit. Usually, Read and Write.
• Random Access Memory (RAM): Time to access memory cells
is independent of their address.
– Not random access:
each of size 16 bits.
• There are 1024 addresses
(0-1023 decimal, or
0000000000-1111111111
binary).
• Reading the word at
address 1021 = 1111111101
we get 1001110100010101
Memory Block Diagram
Memory Block Diagram (cont’)
n
• k address lines are decoded
to address 2k words of
memory.
• Example:
k
• Each word has n bits.
• When Read=1 the n output data contain
the data at the address specified by the
k address lines.
n
• CS enables the memory.
• R/W determines whether memory is read or written.
• When Write=1 the content of the memory at the address
specified by the k address lines is changed to the data
specified by n input data lines.
• 64K = 26·210 = 216 16 address bits
Implementation
Constructing Large RAMs from Small RAMs
• Small memories can be constructed from registers and
combinatorial components. For large memories, other
technologies are used.
• n 8x1 RAMs can be used to construct 8xn RAM
• Example: 8 x 1 RAM
– 8 words of size 1.
– A 38 decoder is used
to enable writing to
exactly one cell.
– An 81 Mux is
used to select the cell
to read.
– Alternatively, use a bus.
• The size of a word stored in memory is 8 bits 8 output bits.
8x3 RAM
3 Addr
Data
8x1 RAM
3 Addr
8x1 RAM
3 Addr
Data
Out
Data
8x1 RAM
3 Addr
Out
Data
CS
CS
CS
R/W
R/W
R/W
CS
R/W
• Actually, no need to duplicate the Decoder.
Out
Constructing Large RAMs from Small RAMs (cont’)
General Purpose Computer
• n 8x1 RAMs can be used to construct 8nx1 RAM
• So far we design digital circuits that perform specific tasks.
This approach is useful for:
– “Simple” tasks resulting in small circuits
– Large numbers of such circuits are required
16x1 RAM
3 Addr
21
Decoder
EN
CS
8x1 RAM
3 Addr
Data
8x1 RAM
3 Addr
Out
Data
CS
CS
R/W
R/W
Out
R/W
bus
• Sometimes it’s better to design a general purpose circuit
(computer), which can perform different sets of instructions
(programs).
• Instructions are:
– Given through input devices
(keyboard, Hard Disk)
– Kept in memory
– Performed by the Central
Processing Unit (CPU)
General Purpose Computer (cont’)
General Purpose Computer (cont’)
• Instructions a typical CPU is capable of performing:
– Data transfer: values can be transferred between
registers in the CPU and external memory.
– Arithmetic: values stored in registers can be combined
using arithmetic operations.
– Logic: values in registers can be combined using logic
operations.
– Shifting the content of registers.
– Testing: the results of operations can be tested to detect
conditions such as overflow, carry, negative result, zero.
– Input/output: values can be retrieved from external
devices or displayed on them.
– Branching: Changing the sequence of executed instruction
during execution.
• Instruction Set Architecture (ISA): The set of instructions
the CPU can perform. This is the lower-level “appearance” of
the computer to a (software) programmer.
Corresponds to Machine/Assembly Language.
• Computer Architecture: High-level description of the
hardware (CPU) that implements the ISA. Usually, divided to
Datapath and Control Unit.
• Datapath: Performs the
data-processing operations.
• Control Unit: Determines the
sequence of operations.
Datapath
Registers file
Control Unit
ALU
System
Datapath Block Diagram
Arithmetic and Logic Unit (ALU)
• The main components of
the datapath are the
Register File and the
Arithmetic and Logic
Unit (ALU).
Carry out
Negative
Zero
Overflow
• ALU: the combinatorial
part that performs the arithmetic and logic operations.
• The operands of the ALU are (the values in) in at most two
registers selected by the control.
• Control signals determine the operation performed by the
ALU.
Implements a variety of
binary (2 operands) and
unary (1 operand)
arithmetic and operations.
• Data bus connects the main memory and the register file.
Datapath: Example
• A possible instruction*:
ADD R1,R2,R3;
(sum the values in R2 and R3
and write the result to R1)
• To implement it:
–
–
–
–
–
–
–
A select = R2
B select = R3
G select = A+B
MF select = ALU
MD select = F
Destination select = R1
Load enable = 1
Instruction Set Architecture
• ISA is the language “understood” by the CPU.
• Every CPU has its own ISA.
• (Software) programmers can use the ISA to write programs to
be executed by the CPU.
• Example:
• Opcode is a binary codeword for the instruction.
• An instruction usually has several parameters.
• Example: 0000101 001 011 010
* Not necessarily a real command.
Subtract
R1 R3
R2
R1  R3 – R2
The Fetch-Execute Cycle
•
The steps perform by the control unit
when executing a program:
1. Fetch the next instruction to be
executed from memory.
2. Decode the instruction:
a combinatorial part that
determines the control signals.
3. Execute the instruction and
(possibly) store the result.
4. Go to step 1.