.
US005200926A
United States Patent [19]
1111 Patent Number:
Iwahashi et a1.
[45]
[54] SEMICONDUCI‘OR INTEGRATED CIRCUIT‘
Date of Patent:
[56]
5,200,926
Apr. 6, 1993
References Cited
[75] Inventors: Hiroshi Inmm, Yokohama; Hideo
U'S‘ PATENT DOCUMENTS
Km, Kawasaki; Yuuichi hm,
Tokyo, an of Japan
4,573,147 2/1986 Aoyama et a1
4,701,889 10/1987 Ando
365/2335
365/2335
4,707,809 11/1987 Ando
.
_
.
.
.
.
4,827,454
[73] Ass‘g’m' “but? Mk
anh'h'b"
mg
a’
-
P
. . . ..
365/2335
365/2335
OTHER PUBLICATIONS
_
IEEE Journal of Solid-State Circuits, vol. SC-22, No.
Jun’ 27’ 1991
5, Oct. 1987, T. Wada et al., “A 34 ns l-Mbit CMOS
SRAM Using Triple Polysilicon”, pp. 727-732.
Primary Examiner-Joseph A. Popek
Division of Ser. No. 568,734, Aug. 17, 1990, Pat. No.
Attorney, Agent, or-Firm--Finnegan, Henderson,
5,056,064, which is a division of Ser. No. 290,721, Dec.
27, 1988, Pat. No. 4,959,816.
Fambcw, Garrett & Dunner
[57]
[30]
365/2335
..... ..
5,056,064 10/1991 Iwahashi et a1. ............... .. 365/2335
Rented U's' Apphamm D.”
[62]
Okazaki
4,959,816 9/1990 Iwahashi et a1.
[21] Appl. No.: 722,530
[22] F?cd'
5/1989
Fmeign Application Priority Dita
Dec. 28, 1987 [JP]
Oct. 7, 1988 [JP]
Nov. 18, 1988 [JP]
ABSTRACT
V
A data transfer control circuit is connected between a
Japan .............................. .. 62330056
Japan .............................. .. 63-252971
Japan .............................. .. 63-291969
891159 ampli?er and Output buffer Circuit The dam trans
fer control circuit is controlled by 111 P1115‘? Signal Sup
plied from a Pulse Signal scncrator so as to have 101151‘-r
delay time which pulse signal is not generated by the
[51]
[52]
Int. CLS .............................................. .. GllC 7/00
US. Cl. .......................... .. 365/2335; 365/ 189.05;
[58]
Field of Seurch ................. .. 365/ 1 89.05, 206, 210,
pulse signal generator, and operate as noise canceller
and prevents from outputting erroneous signal there
365/230_()8
from to the output buffer circuit.
365/233, 233.5, 230.08
10 Claims, 31 Drawing Sheets
[43-24
OUTPUT
23~ BUFFER
ClRCUlT
21~5ENSE
AMPLIFIER
14
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U.S. Patent
'
Apr. 6, 1993
Sheet 1 of 31
5,200,926
OUTPUT
23w BUFFER
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_.__I
cIRcuIT
21~SENSE
AMPLIFIER
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U.S. Patent
Apr. 6, 1993
VDD
291
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Sheet 2 of 31
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21/151’
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. V88
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US. Patent
'
Apr. 6, 1993
Sheet 3 of 31
5,200,926
OUTPUT
23~ BUFFER
CIRCUIT
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4
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US. Patent
Apr. 6, 1993
Sheet 4 of 31
DELAY
CIRCUIT
°DOUT'
SW
F|G.5
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HZI
FIG.6
5,200,926
US. Patent
Apr. 6, 1993
Sheet 5 of 31
5,200,926
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US. Patent
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Apr. 6, 1993
Sheet 6 of 31
5,200,926
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US. Patent
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Apr. 6, 1993
Sheet 7 of 31
54
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US. Patent
Apr. 6, 1993
5,200,926
Sheet 8 of 31
Q~24
OUTPUT
23~ BUFFER
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US. Patent
'
ADDRESS INPUT
SIGNAL (ADD)
Apr. 6, 1993
Sheet 9 of 31
5,200,926
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US. Patent
Apr. 6, 1993
Sheet 10 of 31
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US. Patent
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Apr. 6, 1993
Sheet 12 of 31
5,200,926
OUTPUT
23~ BUFFER
CIRCUIT
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22~ CONTROL
CIRCUIT
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FIG. I8
US. Patent
Apr. 6, 1993
HIGH
Sheet 13 of 31
'
IMPEDANCE
FIG. 19
5,200,926
U.S. Patent
'-
Apr. 6, 1993
Sheet 14 of 31'
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US. Patent
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Apr. 6, 1993
Sheet 17 of 31
5,200,926
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DATA
LATCH
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US. Patent
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Apr. 6, 1993
Sheet 18 of 31
5,200,926
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US. Patent
:
Apr. 6, 1993
Sheet 19 of 31
DATA
5,200,926
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