ECE 301 – Digital Electronics
Counters
(Lecture #20)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Counters
●
A counter is a sequential circuit (aka. finite
state machine) that cycles through a fixed
sequence of states.
●
The state of the counter is stored in Flip-Flops.
●
An n-bit counter
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has n Flip-Flops
–
can cycle through at most 2n states.
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Counters
111
00
11
01
000
110
001
010
10
101
100
011
2-bit Counter
3-bit Counter
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Counters
000
00
01
110
010
101
011
10
2-bit Counter
using only 3 states
3-bit Counter
using only 5 states
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Binary Counters
●
An n-bit binary counter is a counter that cycles
n
through all 2 states in ascending (or
descending) order.
111
000
001
3-bit Binary Counter
110
101
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010
100
Cycles through all 8 states
in ascending order
011
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Binary Counters: Design
1.Draw a state graph that specifies the desired
sequence of the counter.
2.Construct a state table from the state graph.

One Flip-Flop for each bit in the state.
3.Derive a K-map from the state table for each
Flip-Flop input.

Select the type of Flip-Flop to be used.
4.Determine the input equation(s) for each
Flip-Flop.
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Binary Counters: Design
Example: State Table (using D FF)
Present State
C
B
A
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next State
C+
B+
A+
FF Inputs
DC DB DA
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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ECE
Characteristic
Equation:
Q+ = D
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Binary Counters: Design
Example: K-maps (for D FF inputs)
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Binary Counters: Design
Example: Circuit Diagram (using D FF)
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Binary Counters: Design
Example: State Table (using T FF)
Present State
C
B
A
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next State
C
+
0
0
0
1
1
1
1
0
B
+
A
+
FF Inputs
TC TB TA
0 1
1 0
1 1
0 0
0 1
1 0
1 1
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ECE
Characteristic
Equation:
Q+ = T xor Q
Excitation Table:
Q
Q+
T
0
0
0
0
1
1
1
0
1
1
1
0
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Binary Counters: Design
Example: K-maps (for T FF inputs)
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Binary Counters: Design
Example: Circuit Diagram (using T FF)
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Binary Up-Down Counters
What constraints must be placed on the U and D control signals?
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Binary Up-Down Counters
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Loadable Counter with Enable
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Counters: Design
1.Draw a state graph that specifies the desired
sequence of the counter.
2.Construct a state table from the state graph.

One Flip-Flop for each bit in the state.
3.Derive a K-map from the state table for each
Flip-Flop input.

Select the type of Flip-Flop to be used.
4.Determine the input equation(s) for each
Flip-Flop.
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Counters: Design
Example:
Design the following counter using D Flip-Flops.
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Counters: Design
Example: State Table (using D FF)
Present State
C
B
A
Excitation
Equation:
D = Q+
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Next State
C+
0 0 0 1
0 0 1 x
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 x
1 1 0 x
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1 Electronics
0
B+
A+
0
x
1
0
1
x
x
1
0
x
1
0
1
x
x
0
FF Inputs
DC DB DA
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Counters: Design
Example: K-maps (for D FF inputs)
DC
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DB
ECE 301 - Digital Electronics
DA
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Counters: Design
Example: Circuit Diagram (using D FF)
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Counters: Design
Example:
Design the following counter using T Flip-Flops.
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Counters: Design
Example: State Table (using T FF)
Present State
C
B
A
Excitation
Equation:
T = Q xor Q+
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Next State
C+
0 0 0 1
0 0 1 x
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 x
1 1 0 x
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0
ECE
B+
A+
0
x
1
0
1
x
x
1
0
x
1
0
1
x
x
0
FF Inputs
TC TB TA
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Counters: Design
Example: K-maps (for T FF inputs)
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Counters: Design
Example: K-maps (for T FF inputs)
We could derive TC , TB , and TA directly from the state table,
but it is often more convenient to plot next-state maps
showing C+, B+, and A+ as functions of C, B, and A, and then
derive TC , TB , and TA from these maps.
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Counters: Design
Example: Circuit Diagram (using T FF)
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Counters: Design
Example: Next States (for T FF inputs)
Although the original state table for the counter is not
completely specified, the next states of states 001, 101,
and 110 have been specified in the process of
completing the circuit design
101
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110
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Counters: Design
Example:
Design the following counter using JK Flip-Flops.
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Counters: Design
Example: Using JK Flip-Flops
Excitation Table:
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Q
Q+
J
K
0
0
0
x
0
1
1
x
1
0
x
1
1
1
x
0
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Counters: Design
Example: State Table (using JK FF)
Present State
C
B
A
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next State
C+
B+
A+
1
x
0
0
1
x
x
0
0 0
x x
1 1
0 0
1 1
x x
x x
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JC
KC
FF Inputs
JB K B JA
KA
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Counters: Design
Example: K-maps (for JK FF inputs)
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Counters: Design
Example: Circuit Diagram (using JK FF)
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Questions?
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