AUTOMATED LOGIC DESIGN TECHNIQUES APPLICABLE TO
INTEGRATED CIRCUITRY TECHNOLOGY
R. Waxman, M. T. McMahon, B. J. Crawford and A. B. DeAndrade
IBM Components Division, East Fishkill Facility
Hopewell Junction, New York
INTRODUCTION
a non-iterative machine function point of view), the
more part numbers are required. The most versatile
package is a simple logic connective for exa.mple a
NAND; however, the pin-to-circuit ratio is unacceptably high. A way must be found to obtain complex logic packages which do not require an infinite
variety of package types.
A possible solution to the problem is to use Large
Scale Integration (LSI), letting most packages be
customized and still large enough to reduce the quantity of packages in any machine. The customization
of each part leads to inventory problems at the place
of manufacture. In addition, the complexity of each
part may lead to many wiring layers which may be
inaccessible for engineering changes. If an error is
discovered during the fabrication process, the part
may have to be scrapped. This delays delivery and
increases cost of an acceptable part.
Another possible solution is the utilization of chips
or cells having a certain defined logical complexity,
flexibility, and acceptable pin-to-circuit ratio. This
would enable engineering changes and modifications
at the chip or cell level, thus making engineering
changes of the interconnections between cells possible.
The proposed approach described in this paper
is a compromise between a fixed interconnection
pattern and entirely discretionary wiring between
Rapidly advancing integrated circuit technology
has placed many new and often unforeseen demands
on logic packaging techniques and, .hence, is also
impacting traditional computer design concepts. For
instance, one of the most pertinent and immediate
requirements is the. optimum utilization of input/
output (I/O) connections since the package size is
strongly dependent on such connections. The package efficiency is measured in part by the I/O pin-tocircuit ratio, assuming the circuits in a package are
connected in a way to provide an optimum logic
function. Another potential problem to be considered is power dissipation, since integrated circuits
may be contained in extremely small areas.
Consequently, it is imperative for a logic designer
to interconnect .many circuits within a package,
thereby reducing I/O pins, yet' not overburden a
package with more heat than it can safely dissipate
by the cooling provided. The above considerations
are further impacted by the fact that integrated
circuit technology inherently should provide inexpensive circuits. Thus the logic can be reasonably redundant to accomplish the minimum I/O pin-tocircuit objective as well as to minimize package
types. The more versatile a package, the fewer types
are required; the /more functional a package (from
247
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PROCEEDINGS-F ALL JOINT COMPUTER CONFERENCE, 1966
cells on a wafer. That is, the interconnection of
optimized fixed pattern logic arrays may be programmed to nbtain varinus logic functions. Some
related work has been done in this area. For instance, an array of logical elements which are interconnected in a specific pattern has been suggested. 1
Each logical element may be programmed to perform one nf several two-variable functinns by cutting
certain interconnections within each cell. A similar
approach has also been repnrted by AFCRL.2 In
that study it was proposed that each element be a
NOR with possible interconnections to' any or all
eight neighbor NOR's. The interconnectinn pattern
thus determines the functinn that is to be obtained.
The work leads to' speculation that a computerized
approach might lend more sophistication to the
synthesis procedure.
TRADITIONAL COMPUTER DESIGN
PROCEDURE
The traditional procedure in designing a computer
is first to define its major logical sections. The data
flow paths are usually designed initially since they
are generally well defined. Controls and non-iterative
sections are determined last since they are heavily
dependent on data flow organization. In recent
years, the controls have become more organized
through use of read-only memories (i.e., microprogramming) . The read-O'nly memory replaced
much isolated and non-iterative hardware.
The various parts of the computer are still packaged in much the same way as they were first organized on paper. That is, the adders, registers,
shifters,and other iterative networks are packaged
to take advantage of their repetitive occurrence
within the machine. The non-iterative sections are
added without apparent organization.
How is the designer using integrated circuits
presently? He is packaging iterative logical networks
in an attempt to make efficient use of integrated
circuits: These adders, registers, etc. have a high
circuit density relative to the input/output connections to an integrated circuit element. He is packaging unit logic on integrated circuit elements to
satisfy the non-iterative logical sections of a machine.
These elements have a low circuit density relative
to the input/output connections to' an integrated circuit element. In other words, his design philosophy
has not changed but succeeded in locking him into
a pattern that will not permit efficient use of monolithic technology.
How can the designer break out of this pattern?
He is starting to change the pattern by packaging
highly dense one-of-a-kind integrated circuits. This
is efficient from the technology point of view, but
creates inventory problems as well as greater fabrication cost due to the singularity of each part. Large
Scale Integration (LSI) is being used in a manner
which may reduce total parts, but not necessarily
total part types. Problems of inventory and engineering change capability must be overcome. Also being
investigated are the use of logical arrays in matrix
form. Each cell at present is usually a simple logical
connective, which results in an inefficient use of the
elements because of interconnection limitations on
the matrix.
To summarize, the relatively high cost of a component with discrete elements has never permitted
the reduction of total part numbers by designing
with a reasonable amount of redundancy. Although
cost criteria and packaging techniques have changed
today, logic design techniques have not kept pace.
Economy now requires a reduction in parts, but not
necessarily a reduction in logical elements. In fact,
logical element redundancy can be a big factor in
cost reduction if used properly. Efficient packaging
today demands high circuit densities to take advantage of monolithic technology.
MULTIPURPOSE LOGIC CELLS
AS A SOLUTION
An approach adding sophistication to the above
ideas will be described in this study. Engineers already have taken the first step by proposing logical
elements of the AND-OR variety (i.e., AND's feeding OR's). The limitation is that many a designer
has been trained to see AND-OR groupings on the
logic sheet, and that he imposes this AND-OR restriction on logic wherever permissible. He unfortunately is unable to see more complex functions that
are not in the form (AND-OR), used in several
equivalent forms. If he could, he would have available multiple-purpose logic blocks with an efficient
circuit density relative to input! output ports. In an
LSI application, he would have an array with complex yet versatile cells. Wiring of the final interconnection between cells could be one of the last 'steps
of the process, perhaps allowing all personality wiring to be accessible for engineering change. Person-
From the collection of the Computer History Museum (www.computerhistory.org)
AUTOMATED LOGIC DESIGN TECHNIQUES
ality wiring is the wiring of interconnections between
cells which establishes the desired function of the
LSI wafer.
A cellular array built on Large Scale Integration
(LSI) principles would achieve the following objectives:
1. By making each cell a complex function, a large percentage of the wiring
(the wiring of each element) could be
completed before committing the package to its ultimate functional use.
2. By making each cell with a favorable
pin-to-circuit ratio (where pin means
I/O ports from each cell), the final
personality wiring complexity may be
reduced. This enables all personality
wiring to be done on "outside" layers.
3. Reduce the inventory of different parts
(since personality is the last step of the
process) .
4. Throughput to the user is faster since
impersonalized arrays are available
"off the shelf."
5. A mixture of fixed pattern wiring of
cells with discretionary wiring between
cells would result. This would provide
a compromise between long computertime high-wafer yield discretionary
wiring between every circuit, and short
computer-time low-wafer yield fixedpattern wiring between every circuit.
The problem then is this: What logical functions
should complex cell elements generate? This study
describes a tool to aid in determining an optimum
set of multipurpose logic blocks, personalized to a
given computer or set of computers.
249
at the output of this block. For the same input variables, two different functions are available at the
output-the true and complement function. Now if
the input variables are; permuted (i.e., ordered differently on the input leads), it is possible to change
both the output function and the complementary
function into other functions which are, by definition, in the same equivalence class. That is, the
internal circuitry of the block has not changed, but
a different logical function has been obtained simply
by permuting the input variables. If, in addition,
both true and complement are available to the input
(not both at the same time, but whichever one is
needed), more functions both in true and complement form are available at the output. This last
freedom of both true and complementary variables
available at the input (one or the other, but not
both) is reasonable since we are allowing both true
and complement of every function to be available
at the output of the logical block (see Fig. 1).
DESCRIPTOR PROGRAMS
The equivalence class descriptor program generates an identical octal number for any function in
a particular equivalence class. The program is limited to functions of six variables or less. The input
to the descriptor program is the octal number representation of the function column generated from a
NAND BLOCKS
A
THEORY OF EQUIVALENCE CLASSES
The basic theory to be applied to the automated
design procedure proposed in this study is that of
equivalence classes. Another approach might be that
of pattern recognition of logic clusters. However, the
pattern recognition approach lacks the ability to detect logically equivalent functions that have been
laid out in different patterns.
Suppose a logic block existed which could implement a particular function with a given set of variables at its input. Suppose also that both the true
and the complement of that function were available
OR
12: BF
IF
B: C
THEN '2 :
F : A
E : D
:.
INVERT
+ SF + E
~
THE TWO FUNCTIONS ARE IN THE SAME EQUIVALENCE CLASS
Figure 1. Example of equivalence class theory.
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
6-variable truth table. Both the truth table and descriptor programs are written in FORTRAN and
must be run separately due to the limited core storage capabilities of the 1620 computer. Once a logic
cluster has been partitioned out, the computer running time to obtain the descriptor for the cluster is
one to two minutes.
The output of the system is a list of 22-digit octal
numbers which represent the output function for
every cluster partitioned out of the original logic.
By comparing the numbers in the list, it is possible
to obtain the quantity of each equivalence class required to reimplement the original logic.
One of the major constraints of the system is its
limitation of function size to six variables or less.
With the present technique for generating a descriptor by manipulation of truth tables, it is not economical, time-wise, to handle larger functions. A
6-variable true table has 64 rows and 6 columns.
For each additional variable, the size of the truth
table matrix doubles in length and increases one
column. In order to handle a 12-variable function,
the truth table and descriptor programs would have
to manipulate a matrix with 12 columns and 4096
rows. The octal descriptor would have 1366 digits.
Even on a very large computer, the running time for
descriptor generation and comparison would be in
the order of hours for a 100 cluster partitioning.
Also, a 1366 digit descriptor is not the ideal input
to the logic designer who is asked to implement the
function. Storage of a reference table of all functions
with their descriptors is not practical since there are
2n
2 functions of n variables. To overcome these limitations, the following technique to generate an equivalence class type descriptor will be incorporated into
the system. Descriptors for functions of greater than
12 variables can be realized. The descriptor is quite
short and its length is not directly dependent on the
number of variables in the function. There is also a
correlation between the descriptor and the physical
implementation of the logic (see Fig. 2).
The steps for obtaining the descriptor are as follows:
1. Calculate the Boolean expression for
the output of the logic cluster that has
been partitioned out of the original
logic. The expression should be calculated in sum of products form. Either
the true or inverse form of the output
A
F
= ABC + BDEF + AB
DESCRIPTOR = 432
TWO LEVEL IMPLEMENTATION
AND
A
AND
OR
,B
Figure 2. Descriptor example.
expression can be used, depending on
which gives the sum of products form
having the least number of terms.
2. Assign to each term in the expression
a number corresponding to the number
of variables in the term. An illustration is given below:
Function
Descriptor
=
ABC
3
+ DEBF + AG
4
2
3. Permute the digits to give the largest
number; i.e., largest digit first, smallest
digit last. The descriptor resulting from
the function shown in the illustration
will be 432.
Since we are allowing both true and complement
outputs of every function, the bars appearing over
the variables in the Boolean expression do not have
to be accounted for. If an inverted signal is required, the complemented output of the logic block
generating the .signal is used. In the case of the
example given, the physical implementation of the
function could be a 4-way AND, a 3-way AND and
a 2-way AND, all connected to a 3-way OR block.
Thus it is a very simple matter to go from the
descriptor to an actual implementation.
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AUTOMATED LOGIC DESIGN TECHNIQUES
251
It is possible that two functions in the same equivalence class (by the classical definition of equivalence) could have different descriptors. In actual
practice, however, this would occur only a small
fraction of the time. An important advantage of a
descriptor of this type is that many equivalence
classes can be implemented from one descriptor. To
realize this advantage, the logic described by the
descriptor would have to be implemented in two
levels of logic. In the case of the descriptor 432, all
functions having a descriptor of 3 digits, the first
digit being 4 or less, the second digit being 3 or less
and the third being 2 or less, could be realized by
the logic used to implement the 432 example.
THE SYSTEM HARDWARE
An IBM 1620 Mod II Data Processing System
coupled to a 4554 Video Display unit was used to
implement the automated technique. The display has
its own buffer, making it independent of the 1620
as far as maintaining the visual pattern on the CRT.
The logic designer may. communicate with the display unit by use of a light pen or through two sets
of pushbutton switches.
The program and data may be read into the 1620
from cards, or it may be stored on a disk pack and
called by name into the 1620 core storage. Because
of core memory limitations, all programs are stored
on the disk and called into core storage by the main
program when needed.
MAN-MACHINE PARTITIONING TECHNIQUE
The automated technique consists of a general
man-machine interaction program to aid the designer
in partitioning logic to a useful set of multipurpose
logic blocks. It is in a form compatible with a logic
designer's present partitioning method-that is, it
allows a designer to cull out of larger sections of
logic, small partitions that have meaning to him.
The advantage of the automated synthesis technique
is that it results in computer building blocks consistent with technology requirements of Large Scale
Integration without mushrooming part numbers.
A typical application of the system will be described. Reference to Fig. 3 will aid in understanding
the flow through the system. Figure 4 illustrates the
IBM 1620 Mod. II system employed in the automated partitioning technique described in this section.
The first step in the procedure is to generate the
GOOD
It
UNPARTITION
LOGIC
itlNDICATES LIGHT PEN COMMANDS
Figure 3. Flow chart of logic partitioning.
logic preliminary to partitioning it. Initially, the program is ready for a light-pen interrupt. At this point
the designer sees an array of 7 X 7 diamond shaped
dots on the screen. At the bottom of this array is a
set of instructions, as shown in Fig. 5. By firing the
light pen at the touch point adjacent to each instruction, the designer may choose the desired action.
In designing logic, the first step could be to activate
the touch point adjacent to the type of logic block the
designer wished to draw, for example "AND." Once
this has been done, the light pen may be pointed to
any of the diamonds in the 7 X 7 array. As each
diamond in the array is addressed by the light pen,
a logic block will be drawn around it and labeled
as the particular logic function corresponding to the
instruction touch point previously activated (see Fig.
6.). The logic on the screen may be designed by
interspersing AND's, OR's and INVERTERS, or the
designer may work from a pencil sketch and is able
to put on the screen all the AND's followed by all
the OR's, followed by all the INVERTERS, in any
sequence desired.
Once all the logic blocks are on the screen, as
shown in Fig. 7, the designer can point the light pen
at the instruction entitled "DRAW LINES." He may
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
Figure 4. The IBM 1620 Mod. II Data Processing System, coupled to an IBM 4554 Video Display Unit, used to implement the automated logic partitioning technique.
then connect the logic blocks in the desired pattern
by pointing to the end point of each line he wants
drawn (see Fig. 8). The computer program then
draws the lines. When the logic is completely interconnected (Fig. 9), the designer may then point to
the instruction label entitled "LABELS." A box
with labels of one letter will appear on the bottom
of the screen. The initial letter in the box is "A."
The designer may then point to each input he wishes
to label "A." If he wishes to label an input "B,"
he points the light pen to the block with the "A."
The label changes to "B" and all inputs subsequently addressed by the pen will be labeled "B"
(see Fig. 10). He may then continue to label all
inputs down through "z" (Fig. 11).
Should the designer make an error in drawing
the blocks, lines, or labels, there are instruction
touchpoints for erasing blocks, lines, and labels. He
may then go back and draw in the correction by the
appropriate light-pen procedure.
In place of a manual input, the system is capable
of accepting into the disc file up to several thousand
blocks of interconnected logic. Up to 49 blocks of
this stored logic may be placed on the screen at any
one time.
When the logic has been placed on the screen,
the designer may point at the instruction touchpoint
entitled "FUNCTION." When the program is in this
mode, pointing at any block output will . result in
the Boolean function being printed out on the screen
for up to three prior levels of logic; i.e., anylabeled
inputs up to three prior levels, as well as the designation numbers of any blocks feeding the third level
of logic, will appear in the Boolean expression. The
number of variables in the function mode of operation is not limited (Fig. 12).
If the designer desires to partition the logic into
smaller segments, he may point his light pen at the
instruction touchpoint labeled "PARTITION." Then,
by pointing the light pen at the connected logic
blocks which he· desires to partition from the overall
cluster on the screen, he directs the computer which
blocks are to be partitioned. The next operation is to
energize the instruction touchpoint labeled "DRAW
PARTITION." All logic then disappears from the
screen, except for the blocks that were partitioned
out, as shown in Fig. 13. If the function is limited to
six input variables, the touchpoint labeled "TRUTH
TABLE" may be energized.
When the output for the point at which the truth
table is desired is· activated by the light pen, the
octal number representing the truth table will be recorded on a punched card. This information may
then be fed into another program which will deter-
From the collection of the Computer History Museum (www.computerhistory.org)
AUTOMATED LOGIC DESIGN TECHNIQUES
mine the classical equivalence class descriptor of that
function. The function routine may also be used
(Fig. 14). The other approach mentioned earlier
will enable us to obtaIn a descriptor which is not
limited to six variable functions. This unlimited variable descriptor will be incorporated into the system
represented in Fig. 3.
In order to give the designer some idea of how this
partitioning is progressing, he may touch the instruc-
253
tion point labeled "UNPARTITIONED LOGIC."
This restores on the screen all the logic which has
not been partitioned, minus those positions which
have been partitioned out, as shown in Fig. 15. If
for some reason the designer needs to refer to the
overall cluster of logic, he may energize the instruction touchpoint labeled "REDRAW LOGIC." This
will draw all the logic blocks back on the screen with
the partitioned section showing in its original posi-
Figure 5. Light-pen instructions (bottom) and touch points.
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
tion but disconnected from the rest of the logic as
indicated in Fig. 16. If the partition does not meet
some arbitrarily established criteria, the designer may
energize the instruction touchpoint labeled "UNPARTITION." He may then point his light-pen at
Figure 6. Logic block generated by firing light-pen at touch
point.
each of the blocks that have been partitioned out,
energize the instruction touchpoint labeled "REDRAW LOGIC," and the logic will then appear on
the screen with the section that had been partitioned,
reconnected as it was originally displayed. The designer then continues to partition the logic, calling
out the instruction, "UNPARTITIONED LOGIC"
until all the logic on the screen has been partitioned
(Fig. 17).
The designer may operate on larger sections of
logic by means of the touchpoint labeled "SHIFT
LOGIC." The CRT then acts as a window through
which the designer may look at any section of 49
blocks or less of the entire logic stored on the disk.
Once "SHIFT LOGIC" is activated, another set of
instructions appear at the bottom of the screen (see
Fig. 18) which enables the designer to shift the logic
on the screen, to the right or the left the number of
blocks specified. Figure 18 shows the shifting instructions on the bottom of the CRT coupled with the
logic as yet unpartitioned. Figure 19 shows this logic
shifted three columns to the right. The logic for a
complete computer can be visualized as being stored
on a "scroll" which is seven logic blocks high by a
couple thousand logic blocks wide.
All inputs to a 49-block cluster are either labeled
as a primary input with letters or with the designation number of the logic blocks that feed the cluster
(Le., logic blocks on the part of the "scroll" not
visible on the screen). The designer may then go
through the partitioning technique for the cluster
which is being viewed. After partitioning a 49-block
cluster, there will be individual logic blocks around
the edges of the screen (Fig. 20). These were not
partitioned out but are connected to logic appearing
other places upon the logic "scroll." He may then
shift the logic and include these stragglers in partitions with logic blocks to which they are connected
(Fig. 21).
Using the above technique, several hundred partitions may be taken out of the overall machine
logic, their function described by the appropriate
descriptor and the total number of function types
thus greatly reduced. This process may be repeated
by the same designer or by other designers in order
to obtain an optimum set of logical elements to be
used in the implementation of the computer being
designed.
An important advantage of this approach from the
designer's point of view is that it enables the indi-
From the collection of the Computer History Museum (www.computerhistory.org)
AUTOMATED LOGIC DESIGN TECHNIQUES
Figure 7. Complete logic block array generated by light pen.
From the collection of the Computer History Museum (www.computerhistory.org)
255
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
vidual engineer to design as efficiently as possible.
He is not restricted by package limitations or cell
function constraints in his "raw" logic design. The
functions partitioned out by one or more designers
may be evaluated, compared and combined into
efficient multipurpose cells or Universal Logic
Blocks. The cells may then be replaced into the
logic, where the original partitions were removed,
and connected as determined by the descriptor program which is now under development.
APPENDIX
LIBRARY SUBROUTINES
The library subroutines used to change the contents of the buffer, thus changing the pattern on the
CRT, are CHAR and VECT.
CHAR (NX, NY, N, NALPHA, J, L)
NX,NY
x,
N
number of characters to be displayed
NALPHA
name of the array which contains the
message
an index which is incremented by the
amount of buffer positions used to
store message
buffer position where message is
started
J
L
Y coordinates of first character of
message
VECT (NX, NY, NXE, NYE, J, L)
NX, NY
NXE, NYE
J, L
coordinates of start of vector
coordinates of end of vector
as explained for CHAR
The other library subroutines used are:
WAIT
ACT
INACT
CORDNT
CONR 2
Figure 8. Two logic blocks connected by a light-pen using
"DRAW LINES" routine.
Causes machine to stop processing
until there is a light-pen interrupt.
Turns off the mask on the 1620 so
that information from the light-pen
can enter the processor.
Turns the mask on so information
from the light-pen won't interfere
with· the processor.
Determines the x and y coordinates of
the character the light-pen is firing
on.
This subroutine is used by CORDNT
to transfer one word of information
from the display memory to the
From the collection of the Computer History Museum (www.computerhistory.org)
AUTOMATED LOGIC DESIGN TECHNIQUES
DTOC
FEINT
processor memory. The word that
is transferred depends on the character that the light-pen is firing at.
Is a decimal to octal conversion subroutine.
This is another subroutine used by
CORDNT. It provides the processor with the display memory ad-
257
dress and other information (such
as which character is a narrative
word) when there is a light-pen
interrupt.
RESUME
Returns processor control to IR 1.
When there is a light-pen interrupt
control is transferred to IR 3.
When the processor is under con-
Figure 9. Complete logical array interconnected.
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258
QUINK
DISCR
DISCW
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
trol of IR 3 it cannot accept another light-pen interrupt.
Permits programs stored on the
disc in core image to be loaded
into storage much more quickly
than the conventional FORTRAN
'LINK' statement.
Reads information from disk.
Writes information on disk.
Figure 10. One
logic
block
ACKNOWLEDGMENTS
The authors wish to thank Messrs. T. Kameda
and Y. N. Patt for their assistance during the summer of 1965 in obtaining an understanding of the
classification of Boolean functions.
REFERENCES
1. D. Slepian, "On the Number of Symmetry
Types of Boolean Functions of n Variables,"
label~d
using
"LABELS" routine.
From the collection of the Computer History Museum (www.computerhistory.org)
AUTOMATED LOGIC DESIGN TECHNIQUES
Canadian Jour,nal of Mathematics, vol. 5, pp. 18593, 1953.
2. S. W. Golomb, "On the Classification of
Boolean Functions," IRE Transactions on Circuit
Theory, vol. 6 (Special Supplement), pp. 176-86
(May 1959).
3. R. C. Minnick, "Cutpoint Cellular Logic,"
IEEE Transactions on Electronic Computers, Dec.
1964.
259
4. W. F. King III, and A. Guisti, "Can Logic
Arrays be Kept Flexible?" AFCRL Report No. 65547 (Aug. 1965).
5. I. E. Sutherland, "Sketchpad; A Man-Machine
Graphical Communications System," MIT Technical
Report No. 296 (Jan. 30, 1963).
6. D. T. Ross, "Implications of Computer-Aided
Design for Numerically Controlled Production," MIT
Report ESL-TM-212 (Sept. 1964).
Figure 11. Completed logical array labeled.
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
Figure 12. Example of a three-level function from unpartitioned logic.
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AUTOMATED LOGIC DESIGN TECHNIQUES
Figure 13. Partitioned-out cluster of logic.
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
Figure 14. Partitioned-out cluster of logic with output function.
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AUTOMATED LOGIC DESIGN TECHNIQUES
Figure 15. Unpartitioned logic with one partitioned cluster missing.
Figure 16. Logical array with partitioned cluster disconnected.
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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1966
Figure 17. Unpartitioned logic with several partitioned clusters missing.
Figure 18. Logical array shown with "SHIFT" instructions shown at bottom of CRT.
From the collection of the Computer History Museum (www.computerhistory.org)
AUTOMATED LOGIC DESIGN TECHNIQUES
Figure 19. Logical array shifted three columns to the right.
Figure 20. Logic blocks remaining on screen after partitioning.
Figure 21. Logic shifted to the right of screen.
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From the collection of the Computer History Museum (www.computerhistory.org)