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Chapter
5
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5.1 Propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.2 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
“from the ground up” I-2013b --- Copyright  Daniele Giacomini -- [email protected] http://a3.informaticalibera.net
5.3 SR latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.4 Bounce-free switch
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
5.5 Gated SR latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
5.6 SR flip-flop
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
5.7 Time: setup/hold and recovery/removal
5.8 D latch and D flip-flop
. . . . . . . . . . . . . 279
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
5.9 T flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
5.10 JK flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
5.11 Troublesome JK flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . 291
bounce free 269
delay 258
D flip-flop 280
Earle latch 280
edge-triggered 275 flip-flop 257 275 gated D latch 280 hold time
279 JK flip-flop 288 291 latch 257 master-slave 280 memory 257
propagation delay 258
recovery time 279
removal time 279
sequential circuit 257 setup time 279 SR flip-flop 275 SR latch 261
switch 269 transparent latch 280 T flip-flop 286
The combinational circuits transform the input data into the output
data, according to a certain function, without taking into account
any previous status: the data is translated always in the same way,
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after a little amount of time. Because of this characteristic, the combinational circuits are said to be memoryless. Instead, a sequential
circuit takes into account the dynamic on which the input data is received, keeping a status, which is updated by the circuit itself and
which is in fact an additional source of input data that influences the
output result.
The sequential circuits are based on components known as memories, which are made of latches or flip-flops. A latch is a circuit with
some kind of feedback, by which one or more output lines become
input again; a flip-flop is a sophisticated latch which is responsive to
the variation of a data.
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5.1 Propagation delay
Every combinational circuit reacts to the input data variation updating the output with a little time delay, known as the propagation
delay. The amount of the delay time depends on the physical and
mechanical characteristics of the real circuit.
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F
| igure 5.1. An impulse signal traversing a buffer shows on the
output a little delay.
The propagation delay might be used to produce a short impulse, as
the following figure shows.
F
| igure 5.2. A short impulse produced by the delay propagation.
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5.2 Truth tables
The truth table is a way to explain the combinational circuit behaviour, where the output values are shown as functions of the input ones, without considering either the propagation delay or the
dynamic that the input data might have. To explain a sequential circuit behaviour a kind of truth table might be used, but in that case
the notations should be understood depending on the particular context. The following sections introduce latches and flip-flops, which
might be influenced by the input data signal variations, therefore the
following notation is used:
0
stable 0
_/¯ variation from 0 to 1, or positive edge
stable 1
1
¯\_ variation from 1 to zero, or negative edge
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5.3 SR latch
The simplest sequential circuit that keeps its status memory is the
one shown in the following two figures, made either with NOR or
NAND gates. With the NOR gates example, the Q output is initially unknown and might be either 0 or 1; then, asserting the S input (set) even with a short positive impulse, the Q output is asserted
(activated) and it remains active until the R input (reset) remains
negated. That is: a short positive impulse to the S input sets the output, whereas the same impulse to the R input resets the output. With
the example based on NAND gates, the inputs S and R are negated,
so that the set and reset impulse should be negative.
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| igure 5.5. Simple set-reset latch with NOR gates.
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| igure 5.6. Simple set-reset circuit with NAND gates.
The two figures above show a circuit and the corresponding truth
table, which highlights a condition that is not allowed: the NOR circuit should not let both inputs change from 1 to 0 simultaneously,
whereas the NAND one should not let both input change from 0 to
1 simultaneously. The reason for the not allowed condition is explained later.
The above figures represent a simplified version of a kind of circuit
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known as SR latch, which usually has another negated output, Q,
which gets the opposite value of Q.
F
| igure 5.7. SR latch with NOR gates.
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| igure 5.8. SR latch made with NAND gates.
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| igure 5.9. SR latch with NAND gates, changing the meaning of
the input lines.
The SR latch made with NAND gates is equivalent to the NOR one
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with the input ports negated; however, the SR latch with NAND
gates is also used changing the input port names as it is shown in
the last figure above, but this way the behaviour is no more equal to
the NOR gate version, although it is nearly the same. For that reason,
when an SR latch is drawn as a box, it is necessary to specify which
truth table is used; anyway, the SR latch alone is used very seldom
and it is advisable to depict it with logic gates and not only as a box.
F
| igure 5.10. NOR SR latch traces showing two critical situations: the first time both the input ports are asserted and becomes
negated simultaneously; the second time the inputs impulse is
too short.
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The above figure shows a NOR SR latch timing diagram, where the
propagation delay is evidenced, but especially is visible what happens when the input ports drop to zero simultaneously: because of
the propagation delay, the two outputs remains for a while to zero,
but then, as the inputs are now zero, the outputs are activated and
that starts a loop of deactivation and activation. This is the problem
that imposes to avoid to drop to zero the input ports simultaneously.
But even a too short pulse might create troubles: the input impulse
should be long enough to allow the latch to change its state (if that
impulse should change it).
The SR latch is the basis for all other latches and flip-flops; that
is why it is important to know in how many ways it can be implemented, as the following figure shows.
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F
| igure 5.11. SR latch in many equivalent implementations,
where care should be given to the input ports order. On the left
side there are the active-high input versions, whereas on the right
side appear the ones with active-low inputs. The most common
SR latches are highlighted: NOR and NAND.
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5.4 Bounce-free switch
When building real electronic logic circuits, switches are often used,
but in the real world, these components have the ‘bounce’ problem,
which means that opening or closing the switch some unwanted impulses are generated. To avoid these impulses the SR latches are
used, for example in the way shown by the figure below.
F
| igure 5.12. SR latch used to filter the bounces produced by a
switch.
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5.5 Gated SR latches
The SR latch can be extended including two control gates to enable the set-reset input lines. In practice the new SR latch has an
additional input port used to enable the other two inputs: when the
enable input is asserted, the SR latch works as usual, but when it is
negated, the other input lines are just ignored.
F
| igure 5.13. Gated SR latch: when the E input (enable) is asserted, it works as the usual SR latch; when the E input is
negated, the other inputs are ignored. The circuit appears in the
two common versions, together with the usual symbology.
The two diagrams in the above figure are equivalent and it can be
demonstrated with the De Morgan’s laws.
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| igure 5.14. Gated SR latches equivalences.
The gated SR latch does not resolve the resonance triggering prob-
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lem already described: the enable input should be asserted only when
the other inputs are in a valid condition, avoiding the case when both
S and R are asserted at the same time, because when the enable input
becomes negated, it would trigger the resonance.
F
| igure 5.15. Truth table for a gated SR latch, limited to the most
significant cases.
When a gated SR latch is turned on, the initial output status is undetermined. To be able to initialize the circuit it is necessary to extend
the input ports of the internal SR latch, as the following figure shows.
It should be noticed that, depending on the internal SR latch implementation, the initialization signal might be asserted high or low.
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| igure 5.16. Gated SR latch with initialization inputs: when the P
or P input is asserted (preset), the Q output activation is forced;
when the C or C input is asserted (clear), the Q output activation
is forced, clearing the other output port.
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5.6 SR flip-flop
The gated SR latch has an enable input that, when asserted, allows to
receive set and reset assertion from the other inputs, but if the enable
input is to be used as a way to update the latch in a precise moment,
the enable signal must be short enough to avoid that any change can
happen in the meantime. To resolve properly the problem, two gated
SR latches can be connected, one after the other as ‘master’ and
‘slave’, inverting the enable input to the second one: this way the
output of the whole circuit is updated when the enable signal passes
from high to low, that is the negative edge: this kind of latch is a
flip-flop and it might be triggered with a negative or a positive edge,
depending on the implementation.
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| igure 5.17. Positive and negative edges of a signal.
F
| igure 5.18. Negative edge triggered SR flip-flop: when the enable signal goes from 1 to 0, the flip-flop is updated. The circuit
is shown starting from the block diagram and then with the common gate implementations. It should be noticed that the enable
input is now called ‘clock’ and it is usually shown as a triangle.
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| igure 5.19. Negative edge triggered SR flip-flop, with initialization inputs.
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Please notice that the SR flip-flop (positive or negative edge) is never
used; however, the gated latches connected as master and slave might
be used to build more specific flip-flops. Furthermore, instead of a
hypothetical SR flip-flop, the JK flip-flop is used (see section 5.10).
5.7 Time: setup/hold and recovery/removal
There are two significant time intervals related to the synchronous
components, which are the circuits that have a data input controlled
by an enable or clock input line. These time intervals are the setup
time, known with the label t su, and the hold time, known with the
label t h.
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| igure 5.20. Example of correct and wrong conditions, concerning the setup time (t su) and the hold time (t h) constraints.
In different context, when it should be emphasized that the input data
is asynchronous, other names are used: recovery time and removal
time.
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5.8 D latch and D flip-flop
A gated SR latch or an edge triggered SR flip-flop can be connected
so that the R input is equal to the inverted S. This way the single
input line can be called D, for ‘data’, and the new circuit becomes a
D latch or a D flip-flop.
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F
| igure 5.22. D latch and D flip-flop obtained from a gated SR
latch or an edge triggered SR flip-flop.
As for the gated SR latch and the SR flip-flop, the same consideration
about the setup and hold time apply to the ‘D’ variation. But the D
latch do not have invalid combination for the input data that comes
from a single line.
F
| igure 5.23. D latch made with NAND gates. When the E input
is asserted, the circuit receives the data from the Dinput and it
reproduces the same value trough the Q output (inverting that
value at the Q output).
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The D latch can be implemented in more efficient ways, known as
transparent latch and Earle latch, which appear in the following
figure. Please notice that the Earle latch has two complementary enable inputs, E and E, which should be asserted and negated at the
same time, to do their work properly.
F
| igure 5.24. Transparent latch.
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F
| igure 5.25. Earle latch.
The D flip-flop (edge triggered) can be implemented as master-slave,
but there exists an alternative and more efficient circuit that triggers
at the positive edge.
F
| igure 5.26. Master-slave D flip-flop and classical positive-edgetriggered D flip-flop. The timing diagram is related to the second
version that triggers with positive clock edges.
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| igure 5.27. D flip-flops with initialization inputs.
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5.9 T flip-flop
Extending a positive edge D flip-flop it is possible to obtain a T flipflop, where the ‘T’ stands for ‘toggle’. When the T flip-flop receives
the clock edge and the T input is asserted, it inverts the output values.
The truth table uses the notation Q (t) to indicate the Q output value
at the time t and the notation Q (t+1) to indicate the Q output value at
the next clock effective edge.
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F
| igure 5.28. Positive edge T flip-flop: timing diagram and truth
table.
The T flip-flop requires the clear or the preset input ports, because it
is necessary to establish an initial value for the outputs. The following figure shows how to extend a D flip-flop with clear and preset
inputs.
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| igure 5.29. A T flip-flop starting from a D flip-flop, which includes clear and preset inputs.
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5.10 JK flip-flop
Another D flip-flop variation, recalling the SR latch, is the JK flipflop. As for the T flip-flop, the truth table uses notations Q (t) and
Q (t+1), to specify the Q value at the time t or at the next effective
clock edge. In short, the JK flip-flop works like the SR latch, where
J means ‘set’ and K means ‘reset’, but when both J and K inputs
are asserted, the output values are just reversed, like it happens with
the T flip-flop.
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F
| igure 5.30. Positive edge JK flip-flop and truth table.
The JK flip-flop might require the clear or the preset input ports,
but it is not strictly necessary as for the T flip-flop. Anyway, the
following figure shows how to extend a D flip-flop with clear and
preset inputs.
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| igure 5.31. JK flip-flop made as an extended D flip-flop with
clear and preset inputs.
It should be noticed that the T flip-flop is just a JK one with the
inputs J and K connected together.
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F
| igure 5.32. JK flip-flop adapted to work as a T one.
5.11 Troublesome JK flip-flops
Electronic flip-flops (D, JK, T) are currently produced with a specific
technology that is not easily translated into common logic gates. The
JK flip-flop obtained extending the D flip-flop works correctly, but
there are other circuits inside the traditional documentation and data
sheets that if reproduced with a simulator would not work as expected.
The following figure shows the circuit that can be found inside some
original 7476 IC data sheets. This kind of circuit should be positiveedge triggered by the clock signal, but the timing diagram shows
that it does not react this way and after the negative edge the circuit
becomes unstable.
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| igure 5.33. JK flip-flop circuit that does not work.
The following figure shows a master-slave JK flip-flop (negative-
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edge triggered) that is described in the traditional documentation.
This circuit might work, but it does not completely react as expected:
if the J or K input signals are negated before the clock negative
edge, when the clock negative edge actually comes they switch the
flip-flop anyway.
F
| igure 5.34. Master-slave JK flip-flop.
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