Advanced aspects of
combinational and sequential
logics
Michal Lucki
Author: Michal Lucki
Title: Advanced aspects of combinational and sequential logics
Compiled by: České vysoké učení technické v Praze
Faculty of Electrical Engineering
Contact address: Technicka 2, Prague 6, Czech Republic
Inovace předmětů a studijních materiálů pro
e-learningovou výuku v prezenční a kombinované
formě studia
Evropský sociální fond
Praha & EU: Investujeme do vaší budoucnosti
EXPLANATORY NOTES
Definition
Interesting
Note
Example
Summary
Advantage
Disadvantage
ANNOTATION
The goal of this module is to present particular design steps of achieving a sequential logical
circuit by using a TTL series. The idea how to assign the pins of selected flip-flops to solve
practical tasks is presented. Last but not least, the procedure of specifying the address and
data ports of a multiplexer is presented in more details.
OBJECTIVES
After studying this module, a student should know the entire design process of sequential
logical circuits. It should be able to decide, what components are the most suitable for
practical implementation. A student should be familiar with a TTL series of integrated circuits
and should know the operation of memory elements. The basic knowledge on combinational
and sequential logics is assumed (the procedure of creating the state diagrams and transition
tables, as well as the minimization of Karnaugh maps).The students should be able to solve
practical tasks, which should be finalized by specifyingthe logical functions implemented by
using flip-flops. Last but not least, the goal of this module is to learn how to address the ports
of multiplexers in order to simplify the final appearance of designed circuits.
LITERATURE
[1]
GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the
Logic of Sets, IEEE Press Understanding Science & Technology Series, Mar 16, 1998
[2]
STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and
Automata: Towards Modern Information Technology (Studies in Computational
Intelligence), Springer, Mar 7, 2011, ISBN-10: 3642116817
[3]
HASSOUN, S., SASAO, T.: Logic Synthesis and Verification (The Springer
International Series in Engineering and Computer Science), Kluver Academic
Publisher, Nov. 1, 2001, ISBN-10: 0792376064
[4]
HACHTEL, G., SOMENZI, F.: Logic Synthesis and Verification Algorithms, Springer,
Feb 10, 2006, ISBN-10: 0387310045
[5]
KOHAVI, Z., JHA, N.: Switching and Finite Automata Theory, Cambridge University
Press, 2009, ISBN-10: 0521857481
[6]
HOLDSWORTH, B., WOODS, C.: Digital Logic Design, Fourth Edition, Dec. 17,
2002, Integra Software Services, UK Printed, ISBN-10: 0750645822
[7]
Nelson, V., Nagle, H., Carroll, B., Irwin, D.: Digital Logic Circuit Analysis and Design,
Mar 18, 1995, ISBN-10: 0134638948
Index
1 Design of a sequential finite state machine by using memory elements .......................... 6
1.1
Design of a finite-state synchronous machine – task ................................................. 6
1.2
Design of a finite-state synchronous machine – state diagram and a transition table 7
1.3
Design of a finite-state synchronous machine – minimization and encoding ............ 8
1.4
Transistor-transistor logic series (1/3) ........................................................................ 9
1.5
Transistor-transistor logic series (2/3) ...................................................................... 11
1.6
Transistor-transistor logic series (3/3) ...................................................................... 12
1.7
Transitions of a D-type flip-flop .............................................................................. 13
1.8
Transitions of a JK flip-flop ..................................................................................... 14
1.9
Design of a finite-state synchronous machine – specification of D flip-flop (1/2) .. 15
1.10
Design of a finite-state synchronous machine – specification of D flip-flop (2/2) .. 16
1.11
Design of a finite-state synchronous machine – solution for a JK flip-flop (1/2) .... 17
1.12
Design of a finite-state synchronous machine – solution for a JK flip-flop (2/2) .... 18
2 Specification of address and data ports of a multiplexer for practical implementations19
2.1
Practical use of a multiplexer (1/2) .......................................................................... 19
2.2
Practical use of a multiplexer (2/2) .......................................................................... 20
2.3
Specifying the address ports of a multiplexer (1/2) ................................................. 21
2.4
Specifying the address ports of a multiplexer (2/2) ................................................. 22
2.5
Specifying the information ports of a multiplexer (1/3)........................................... 23
2.6
Specifying the information ports of a multiplexer (2/3)........................................... 24
2.7
Specifying the information ports of a multiplexer (3/3)........................................... 25
2.8
Final arrangement of a multiplexer .......................................................................... 27
3 Case study. Complete practical design of an optimal sequential finite state machine 28
3.1
Task – design of a controller for a locker ................................................................. 28
3.2
Encoding and minimization of transition tables ....................................................... 29
3.3
Minimization of Karnaugh maps (1/2) ..................................................................... 30
3.4
Minimization of Karnaugh maps (2/2) ..................................................................... 31
3.5
Specification for used 8-bit multiplexers (1/2)......................................................... 32
3.6
Specification for used 8-bit multiplexers (2/2)......................................................... 34
3.7
Conclusion ................................................................................................................ 35
4 Final test .............................................................................................................................. 36
1 Design of a sequential finite state machine
by using memory elements
1.1 Design of a finite-state synchronous machine
– task
Design a controller for a trolley operating on three containers S1, S2, and S3, as
displayed in the figure. The containers must be supplemented by some material.
The containers are equipped with sensors x1, x2, x3, indicating the level of material
in particular containers. Logical “1” signalizes the low amount of material and the
demand for service. If every container indicates the low amount of material, the
service should be provided in series: S1, S2, S3, S1, S2, S3, S1… If two of three
boxes are empty, the service is provided alternately: Sa, Sb, Sa, Sb, Sa… If one of
three boxes is empty, provide a service to it. 4) If no sensor is active, there is no
action.
Specification of internal states and the outputs
There are four internal states corresponding to possible positions of a trolley.
When the trolley is in its initial position and there is no service to the containers,
the outputs are 000. Servicing the first container forces the outputs to 100.
Servicing the second container forces the outputs to 010. Servicing the third
container forces the outputs to 001.
The outputs are set based on the internal states of the machine. New values at the
inputs (which is the signal from the sensors X1, X2, and X3) do not affect the
outputs directly. A state diagram shows that we deal with a Moore machine.
Assumed knowledge: a student should be familiar with the fundamentals presented in the previous modules
entitled „Fundamentals of combinational logics“ and „Principles of sequential logical circuits“. Basic
knowledge on Boolean algebra, operation of logical gates, interpretation of truth tables, Karnaugh maps,
creation of state diagrams and transition tables or the principle of operation of a simple multiplexor or a latch
is assumed. Based on this knowledge, we present the entire process of obtaining particular design stages
implementing the Transistor-Transistor Logic components.
1.2 Design of a finite-state synchronous machine
– state diagram and a transition table
State diagram
The state diagram can be rewritten into a transition table. Particular rows
correspond to different internal states (A) and their transitions to the next values
(A’).
Table of transitions
Notice that the clock period should be long enough to complete the service of
a container. Although S1 is much closer than S3 to the initial position of a trolley,
time given for a service is identical, which might be found as not effective.
7
1.3 Design of a finite-state synchronous machine
– minimization and encoding
We recommend the students to verify that the obtained transition table is minimal
and no states are redundant. You can check it by using so-called triangle tables,
described in details in the module “Principles of sequential logical circuits”.
The internal states can be represented by binary code words of Gray code, thus
creating Karnaugh maps to be minimized.
Depending on the amount of internal states, we turn it into 2-bit or 3-bit or, in
general, n-bit code words. The internal variable (for example A, B… or 1, 2, 3)
can be turned into Q1, Q2,… (and their next states A’, B’ etc. are turned into Q1’,
Q2’…). Since there are four internal states: 0, 1, 2, 3, the combinations of two bits
(Q1Q2) are sufficient. States (A) are then encoded (into Q1Q2), as follows:
0→00, 1→01, 2→11, 3→10
The transition table can then be rewritten by replacing A by Q1Q2, A’ by Q1’Q2’
as well as by replacing 0, 1, 2, and 3 by using 00, 01, 11, 10.
Encoded transition table for the specification of variables assigned to memory elements
Bold values indicate the transition. When you look at the most left-hand columns
containing actual values of Q1Q2 and the considered field containing next Q1’Q2’
values, you can see, whether there is transition to a new value or not (change from
0 to 1 or from 1 to 0). If it is so, the new value is in bold. Then you don’t have to
check the left-hand column.
The above table can be split into two factual Karnaugh maps, one for Q1’ and
another one for Q2’. Both can be solved separately to result in final formulas for
Q1 and Q2 functions, as well as for the corresponding outputs Y1, Y2 and Y3.
8
1.4 Transistor-transistor logic series (1/3)
Specification of memory elements for practical
implementation
The next step is to specify memory elements used for their practical
implementation. We obtained n Karnaugh maps for n functions of Q, which can
represent the pins of a flip-flop (in general, any component with internal
memory), such as flip-flops.
We can use D-type flip-flop, JK flip-flop or more advanced memory elements,
such as arithmetic logical units. The number of Q variables (Q1, Q2, …Qn) means
that you must use n flip-flops.
To solve this step, the knowledge on internal transitions of flip-flops is required. We consider a D-type flipflop and a JK flip-flop, of which the principle of operation is known from the previous teaching modules on
digital engineering.
To implement the specified functions, we can use components from a TTL
(Transistor-transistor logic) series of integrated circuits, which comprise gates
arrangements, latches, flip-flops, shift registers or counters. Based on the obtained
functions, the goal is to connect the particular pins of the integrated circuits.
Here is the list of selected integrated circuit labeling. Those are just selected items
from a list containing many types or memories, arithmetic logic units, registers,
counters, modulo counters, code converters.
•
7400 – four pieces of 2-input NAND gates
•
7402 – four 2-input NOR gates
•
7410 – three 3-input NAND gates
•
7420 – two 4-input NAND gates
•
7430 – 8-input NAND
•
7474 – D-type flip-flop
•
7485 – binary 4-bit comparator
•
7489 – RAM memory for sixteen 4-bit words
•
7490 – decimal counter
•
7491 – SISO register
•
7493 – 4-bit binary counter
•
74107 – two JK flip-flops
•
74150 – 16-bit multiplexer
9
•
74151 – 8-bit multiplexer
•
74151 – two 4-bit multiplexers
•
74164 – SIPO, SISO registers
•
74165 – SISO, PISO
10
1.5 Transistor-transistor logic series (2/3)
Here are the selected items from the TTL series of integrated elements for
practical implementations. The interest is focused on memory elements and
components used for multiplexing signals in more complicated arrangements.
A very popular four 2-input NAND gates. 7400 in a TTL series of integrated circuits
D-type latch pin organization. 7474 in a TTL series of integrated circuits
11
1.6 Transistor-transistor logic series (3/3)
Here are the selected items from the TTL series of integrated elements for
practical implementations. The interest is focused on memory elements and
components used for multiplexing signals in more complicated arrangements.
Double 4-bit multiplexer (each 4 information ports C0-C3, and two address ports A and B). 74153
in a TTL series of integrated circuits
8-bit multiplexor (eight information inputs D0-D7 and three address ports A, B, C) 74151 in
a TTL series of integrated circuits
12
1.7 Transitions of a D-type flip-flop
A D-type flip-flop can be referred to as a register. Data appears to be loaded when
a transition, or edge, occurs on the clock input, which is therefore said to be edgesensitive (it is loaded when “an edge occurs”). A transition from 0 to 1 is known
as a rising-edge or a positive- edge.
Some flip-flops have an additional input called ~clear, which forces q to 0,
irrespective of the value on the data input. Similarly, some flip-flops have a preset
input, which forces q to 1, and some have both. These inputs may be either
asynchronous or synchronous. In the more common asynchronous case, the effect
of ~clear going active is immediate and overrides both the clock and data inputs
(the effect of this input is not synchronized to the clock). By comparison, in the
synchronous case the effect of ~clear is synchronized to the active edge of the
clock.
Internal transitions of a D-type flip flop, useful for specifying the states of D from the Karnaugh
map containing the values for Q and Q’
For example, if an implementation with a D-type flip-flop is assumed, we need to
find the states of D, based on the transitions of Q1 to the next Q1’. Similarly, for
a JK flip-flop, we need to predict the values of J and K, based on the internal
transitions. The transition tables for selected memory elements are, as follows.
13
1.8 Transitions of a JK flip-flop
When both the j and k inputs are 1, an active edge on the clock causes the outputs
to toggle to the inverse of their previous values.
Internal transitions of a JK flip flop, useful for specifying the states of J and K from the Karnaugh
map containing the values for Q and Q’
Please, note that the transitions of a D-type flip-flop are much more “user
friendly”, since the value of D is practically the same as the value of Q’ for every
line in a transition table.
In JK flip-flops, one must solve two times more Karnaugh maps (because instead
of one D port, there are two separate ports: J and K). In addition, relations
between J, J and Q’ is more complicated.
14
1.9 Design of a finite-state synchronous machine
– specification of D flip-flop (1/2)
Let us go back to the encoded Karnaugh map for the controller of a trolley in our
example.
Encoded transition table for the specification of variables assigned to memory elements
We assume using a D-type flip-flop. We must use two flip-flops (we consider
pairs: Q1-D1, Q2-D2). Having the knowledge on the resultant value of D pin
based on transitions from Q to Q’, we can redraw the Karnaugh map using D
instead of Q1’.
Separate Karnaugh map for D1, based on the table for Q1’ and the transition table of a D-type flipdlop
Please, note that obtaining the value of D is the simplest, since D value is identical
to Q’. Then the Karnaugh map for D is identical as the one for Q’.
The final appearance of a D1 function is following:
D1= X 2 X3| Q1Q2 X3| Q2 X1| Q1 X1| X1 X 2
15
1.10 Design of a finite-state synchronous
machine – specification of D flip-flop (2/2)
The same is obtained for another flip-flop:
Separate Karnaugh map for D2, based on the table for Q2’ and the transition table of a D-type flipdlop
D2 = Q1Q2 X 2 X 3| Q1Q2 X 3| Q1Q2 X 2| X1 X 3| X1 X 2
We also derive the functions of outputs.
In a Moore machine, outputs depend only on the internal states (only Q, not X).
We look into the Karnaugh map to create the relation between Y and Qs (Q1Q2).
We can create small maps containing the relations between those Qs and Y only.
In our particular care, we obtain:
Y1 = Q1 Q2
Y 2 = Q1 Q2
Y 3 = Q1 Q2
We specified the pins for a D-type flip-flops (Qs, Ds) and the outputs.
Finally, we specified all the necessary functions (D1, D2, Y1, Y2, Y3) to create
the final appearance of a sequential circuit using memory elements necessary for
the internal states.
16
1.11 Design of a finite-state synchronous
machine – solution for a JK flip-flop (1/2)
For better comprehension, we also present the solution for a JK flip-flop.
Obtaining J and K needs to modify the Karnaugh map.
For example, if there is bold 1 in a Karnaugh map, it means there was a transition
from 0 to 1 (you can check it by comparing the first column for Q and the actual
field containing the value of Q’), then we force the value in the considered field to
be 1, as according to the transition table of a JK flip-flop.
In addition, we must prepare two times more tables than for D; one for J and
another for K.
Karnaugh map for J1, based on the table for Q1’ and the transition table of a JK-type flip-dlop
J1= Q2 X3| X 2 X3| X1
Karnaugh map for K1, based on the table for Q1’ and the transition table of a JK-type flip-dlop
K1= X1 X3| Q2 X 2| X1 X 2
17
1.12 Design of a finite-state synchronous
machine – solution for a JK flip-flop (2/2)
Karnaugh map for J2, based on the table for Q1’ and the transition table of a JK-type flip-dlop
J 2 = Q1 X3| Q1 X 2| X1 X3| X1 X 2
Karnaugh map for K2, based on the table for Q1’ and the transition table of a JK-type flip-dlop
K2 = X 2 X3| X1 X3| Q1 X1| X1 X 2
The outputs Y1, Y2, and Y3 are obviously the same, since they do not depend on
D, J, K, but on Qs.
18
2 Specification of address and data ports of
a multiplexer for practical
implementations
2.1 Practical use of a multiplexer (1/2)
Brief description of a principle of operation of a simple multiplexer was presented
in the module on combinational logics.
Since the function is expressed as a sum of products, the implementation would
eventually require the number of NAND gates, which is not an optimal solution.
Reading and comprehension of operation from such a scheme is not always easy
and transparent.
We can use multiplexors instead. For this reason, in the following sections, we
focus on specifying of address and information ports of a multiplexor.
For example, for up to six variables, a 4-bit multiplexer is suitable. For more than
six up to eleven, an 8-bit multiplexer is suitable, and so on.
Here I present the procedure, how to select information and address ports of
a multiplexer, and how to assign the appropriate functions to them to finally
connect the corresponding pins in a TTL component.
Assume a logical function comprising n variables. The names of variables can be
any.
Let’s consider five variables Q1, Q2, Q3, X1, X2. (I use such names of variables
thinking about future association with Q pins of a flip-flop).
19
2.2 Practical use of a multiplexer (2/2)
A pair of two 4-bit multiplexers is contained in a 74153 circuit of a TTL series. It
has two address ports and 4 information (data) ports.
Double 4-bit multiplexer (each 4 information ports C0-C3, and two address ports A and B). 74153
in a TTL series of integrated circuits
The concerned function named D could be specified as a sum of products
comprising those variables:
D = Q1 Q2 X 2| X1| Q1 Q3 X 2| X1 X 2
Such a function could be implemented by using primitive gates (looking like a big
mass…) or… by using a 4-bit multiplexer.
First, we split the function to particular products, studied separately:
Q1 Q2 X 2
X1
Q1 Q3 X 2
X1 X 2
20
2.3 Specifying the address ports of a multiplexer
(1/2)
We write down all the variables in one line.
We consider the first product and put a “1” below the variable if it is contained in
the product, a “0”, if it is contained in the product, but it is negated, and “-“, if it is
not present in the product.
For first product
Q1 Q2 X 2
we obtain:
Gradual filling out the table to specify ports of a 4-bit multiplexer (general principle apply also to
8-bit multiplexers)
For the remaining products, the table is filled gradually and looks, as follows:
Table containing information on potential address and data ports of a multiplexer
21
2.4 Specifying the address ports of a multiplexer
(2/2)
We count the number of “0s” and the number of “-“ in every column of the
created table. The expression 2,1 means that the column contains two “-“ and one
“0”:
Specification of the number of log0 and “-“ states in particular columns
Now the goal is to select address (“select”) ports.
A 4-bit multiplexer has two address ports (a, b). It has also four information (data)
ports (C0-C3).
We select the two columns, in which we have the maximum number of “0” and
the minimum number of “-“. A variable described by this column becomes an
address ports.
In case that more columns are suitable (the resultant number of “-“ and “0” is the same), we just use some of
the most suitable variables by random or intuitive selection.
In our example, Q1 and X2 become address ports.
Selecting the address ports of a multiplexer
22
2.5 Specifying the information ports of
a multiplexer (1/3)
Having this assumption on mind, we must specify the information (data) ports by
using the following diagram.
It contains four columns, since a 4-bit multiplexer contains four information (data)
pins (C0-C3). C0-C3 ports are associated to binary strings 00, 01, 10, 11.
Notification: an 8-bit MUX contains 8 data ports associated to 3-bit strings 000,
001, 010,…).
We put the same amount of horizontal lines as the number of rows in the diagram
for the address ports.
Beginning of a process of specifying data ports of a multiplexer
We consider the first line.
We put a cross on that column, which expresses the values specified in address
ports for the same line.
For example, in the first line, address ports exhibit 10 (see the left-hand diagram
below), then we mark C2 column (data port), which is associated with 10 (see the
right-hand diagram). Address ports in the second line express “- -“ in the left-hand
diagram, which correspond to any 2-bit binary combination, so we put a cross on
every column in the second line of the right-hand diagram.
23
2.6 Specifying the information ports of
a multiplexer (2/3)
Specifying the values for data ports C0-C3 of a multiplexer
Specifying the values for data ports of a multiplexer - progress
The final appearance of a diagram for data ports is, as follows.
The final appearance of a diagram for data ports
24
2.7 Specifying the information ports of
a multiplexer (3/3)
Finally, we must give the functional description of data ports.
We go back to the diagram for address ports and look at variables associated with
data ports (here: Q2, Q3, and X1). We ignore Q1 and X2 because they are not data
variables; they were used as address variables.
For C0 pin, we have a cross in the second and fourth line. We consider the second
and fourth line in the left-hand diagram, for which we obtain
{Q2 Q3 X 1} = {− − 1} and {− − 1}
Specifying the functional description of data port C0
C0 is then specified by the function being the sum of products generated from the
particular lines in the left-hand diagram:
C0 = X1| X1 = X1
In the similar fashion, we specify C1:
Specifying the functional description of data port C1
The obtained functional description of all the data ports is, as follows:
C1 = X1| Q3
The remaining data ports are:
25
C2 = Q2| X1| X1 = Q2| X1
C3 = X1
Address ports has already been specified as:
A = Q1
B = X2
26
2.8 Final arrangement of a multiplexer
The operation of a multiplexer implementing the function:
D = Q1 Q2 X 2| X1| Q1Q3 X 2| X1 X 2
Can be expressed in an abbreviated form as:
D = MUX (C0, C1, C2, C3; A, B)
Where C0-C3 are data ports, A and B are address ports. In our example they
become:
D = MUX ( X1, X1| Q3, Q | X1, X1; Q1, X 2)
Notification: the above procedure shows the mindfulness of selecting the address
ports for columns with minimum number of “-“ and maximum number of “0s”.
Then, the functions for data ports are the simplest.
The arranged multiplexer implementing the function given at the begining of this
task
D = Q1Q2 X 2| X1| Q1Q3 X 2| X1 X 2
is, as follows (we use a standard TTL circuit known as 74153):
The arranged multiplexor implementing the given function
27
3 Case study. Complete practical design of
an optimal sequential finite state machine
3.1 Task – design of a controller for a locker
Design a controller for a locker, which opens the locker by using two buttons.
When a button is pressed or hold, a variable associated with it is logical 1.
Revealed button means logical 0. The right sequence for opening is 00, 10, 00, 01,
00. The wrong combination pressed from the keyboard is responsible for an alert.
The right combination opens the locker. Once it is opened, any combination of
buttons pressed does not affect the locker, it remains opened.
There are two input variables a and b corresponding to two buttons at the
keyboard.
We specify outputs:
1, unlock it
Y1 = 
 0, locked
1, alert (alarm)
Y2 = 
0, no alert
State diagram:
State diagram of the designed controller
28
3.2 Encoding and minimization of transition
tables
The following step is encoding the obtained transition table by using the Gray
code in order to minimize the Karnaugh maps.
We recommend the readers to verify that this table is minimal. You can use a triangle table.
Transition table with the internal states of a locker’s controller
Encoded transition table. We add two more rows 101 and 100, which are not
covered by the states, however, they are necessary to complete the Karnaugh map:
Encoded transition table
29
3.3 Minimization of Karnaugh maps (1/2)
Karnaugh maps for three D flop-flops:
Karnaugh map for D1
D1 = Q1| Q2 b | a b | Q2 a | Q2 Q3 b
Karnaugh map for D2
D2 = Q2| b | Q3 a
30
3.4 Minimization of Karnaugh maps (2/2)
Karnaugh map for D3
D3 = Q1 Q3| Q2 b | Q1 a | Q3 b
Karnaugh maps for the outputs obtained from the transition table:
Karnaugh maps for the outputs
Y1 = Q1 Q3
And
Y 2 = Q1 Q3
We already obtained the functional description of D1, D2 and D3 ports of the
three flip-flops.
31
3.5 Specification for used 8-bit multiplexers
(1/2)
We already obtained the functional description of D1, D2 and D3 ports of our
three flip-flops. To avoid the big amount of NAND gates for loading Qs and a and
b to the D port of flip-flops, we specify ports of an 8-bit multiplexer to implement
these functions. I justify some of them for better comprehension.
Specifying the address and data ports of and 8-bit multiplexer for D1
U 0 = Q1
A red cross is in the first line for U0 in the right-hand diagram. Then we look into
the first line of the left-hand diagram, where we check the information ports being
Q1 and Q3. Q3 is 1.
U1 = Q1|1 = 1
Anything added to 1 result in 1.
A red cross is in the first and the second line. Corresponding information ports in
the first line are U1 =1
In the second line we find “-“, which means that logical 1 is added to the result
obtained for the first line.
U 7 = Q1|1|1 = 1
The same situation as for U0.
U 3 = Q1|1|1 = 1
U 4 = Q1| Q3
Why? The cross is put into the first and the last line in the right-hand diagram. We
look into the first line of a left-hand diagram (we obtain Q1) and the last line,
where Q3 is zero, so the variable will be negated in the final formula.
32
U 5 = Q1
U 6 = Q1|1| Q3 = 1
U 7 = Q1|1|1 = 1
The MUX function for an 8-bit MUX is similar to the one of a 4-bit MUX from
the previous screens.
D1 = MUX (U 0, U1, U 2, U 3, U 4, U 5, U 6, U 7; A, B, C)
in our example become:
D1 = MUX (Q1,1, Q1,1, Q1| Q3, Q1,1,1; Q2, a, b)
33
3.6 Specification for used 8-bit multiplexers
(2/2)
Specifying the address and data ports of and 8-bit multiplexer for D2
D1 = MUX (Q3,1, 0,1,1,1,1,1; Q2, a, b)
In other literature sources, information ports of an 8-bit multiplexer are labeled
not as U0-U7, but as D0-D7. However, this is confusing, since D is reserved for
a D flip-flop.
In the same way we would proceed for D3min, we recommend the reader to try it
at home.
D3 = MUX (a, Q2| a,1, Q2| a, 0, Q2,1,1; Q1, Q3, b)
The obtained controller is implemented by using TTL components containing Dflip-flops or 8-bit multiplexer. (TTL stands for transistor-transistor-logic).
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3.7 Conclusion
We have completed the content of lectures. I hope you familiarized with the
procedure of logical circuits design.
When you want to make your controller work fast and be cheap, TTL components
are suitable.
We focused on the knowledge that can apply not only to integrated circuits, but
also to microprocessors or arithmetical logical units, where instead of connecting
particular pins physically, you write a program specifying paths to activate the
required function.
The knowledge of the principles of internal operation of logical components as
well as the properties of logical functions is very universal, because the principle
of operation of multiplexers, latches, registers or memories designed in any
technology uses those basic approaches. Thanks to that course you learned, what
are the internal operations at the level of particular bits, not only how does the
device appear to an external world. This will help you design any device using
any technical solution. The theory of logical functions and Boolean algebra will
always be valid. It is like basic mathematics.
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4 Final test
Please, verify your knowledge by solving the following final test.
1. Log1 added to any value results in
a) Log0
b) Log1
c) Log0 or Log1 depending on the fact, if you are adding a+b or b+a, where
a and b are tvo variables to be added
d) Log2
Solution: b
2. Design stages of sequential logics, listed chronologically, are, as follows:
a) state diagram, transition table, triangle table, minimization process, encoding,
specification of memory components
b) transition table, selection of memory elements, Karnaugh map, specification
of non-contradicting states, state diagram
c) selection of logical components, conversion from Mealy machine to Moore
machine, minimization of Karnaugh table, state diagram
d) transition table, assignment of addres ports of a multiplexer, state diagram,
triangle table, Karnaugh maps
Solution: a
3. What steps are always included in the design process of a sequential
machine and shouldn't be skipped:
a) minimization process, encoding, assignment of addres ports of a multiplexer
b) state diagram, transition table, conversion from Mealy machine to Moore
machine
c) state diagram, transition table, specification of memory components
d) state diagram, specification of non-contradicting states, solving Karnaugh
maps, assignment of addres ports of a multiplexer
Solution: c
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4. What is TTL?
a) Texas Technology Logic
b) Transistor-Transistor Logic
c) Time-to-Time Logic
d) Transition-Table Logic
Solution: b
5. D-type flip-flop
a) can be referred to as a modulo-16 counter
b) loads data when a transition, or edge, occurs on the clock input
c) multiplexes or demultiplexes digital signals
d) is labeled as 7400 in a TTL series
Solution: b
6. 4-bit multiplexer from a TTL series has
a) 3 address ports and 3 data ports
b) 4 address ports and 2 data ports
c) 2 address ports and 2 data ports
d) 2 address ports and 4 data ports
Solution: d
7. 8-bit multiplexer from a TTL series has
a) 3 address ports and 8 data ports
b) 8 address ports and 2 data ports
c) 2 address ports and 8 data ports
d) 4 address ports and 7 data ports
Solution: a
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8. What elements are the basis to implement the transitions (internals states)
of a sequential machine?
a) coders
b) NAND gates in a loop
c) flip-flops
d) multiplexers
Solution: c
9. What is the goal of encoding the transition table?
a) to distinguish between input and internal varialbes
b) to find redundant variables
c) to transform it into a Karnaugh map
d) to transform it into a truth table
Solution: c
10. Karnaugh map
a) is used to minimize logical functions
b) is named after Thomas Carnaugh
c) cannot contain don’t know states
d) cannot cover more than 3 variables
Solution: a
11. What information is contained in a state diagram?
a) transitions between states
b) values of input variables
c) output values
d) values of internal variables
Solution: a, b, c, d
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12. What is the advantage of using the multiplexers in practical
implementations?
a) less number of gates in the arrangement
b) more transparent connections
c) better performance
d) asynchronic regime of operation
Solution: a, b
13. Moore machine
a) has infinite number of states
b) determines new outputs only when the internal state is updated
c) can determine new outputs immediatelly by new input values
d) set output synchronously with respect to clock
Solution: b, d
14. Transition table
a) is a form of representation of transition between particular states of a machine
b) is a canonic form of a logical function
c) is a table with minimal logical functions
d) specifies true or false for given operands and/or internal variables
Solution: a, d
15. State diagram
a) is a form of representation of transition between particular states of a machine
b) is a canonic form of a logical function
c) is a diagram with minimal logical functions
d) provides an overview on outputs, operands and/or internal variables
Solution: a, d
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16. In sequential logics:
a) one combination of operands can be assigned different outputs
b) actual state of outputs depends on actual inputs
c) actual state of outputs depends on past states
d) internal states are introduced to keep the information required to determine
outputs
Solution: a, b, c, d
17. What sentences are true?
a) JK flip-flop requires to solve more Karnaugh maps that D-flip-flop
b) to obtain the output function (Y) of a Moore machine, you should solve
a Karnaugh map containing input variables and internal variables
c) to obtain the output function (Y) of a Mealy machine, you should solve
a Karnaugh map containing input variables and internal variables
d) multiplexer is a memory element (can store internal variables)
Solution: a, c
18. What are the transitions of a D-type flip-flop?
a) When Q->Q' is 0->0, D is forced to 0
b) When Q->Q' is 0->1, D is forced to 1
c) When Q->Q' is 1->0, D is forced to 0
d) When Q->Q' is 1->1, D is forced to 1
Solution: a, b, c, d
19. What are the transitions of a JK-type flip-flop?
a) When Q->Q' is 0->0, JK is forced to 0b) When Q->Q' is 0->1, JK is forced to 1c) When Q->Q' is 1->0, JK is forced to -1
d) When Q->Q' is 1->1, JK is forced to -0
Solution: a, b, c, d
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20. What signals are the most suitable to be assigned to address ports of
a multiplexer?
a) Those exhibiting the minimum number of log0
b) Those exhibiting the maximum number of don't occur „-“ states
c) internal variables
d) input variables and variables with the feedback
Solution: a, b
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