Chapter 2
Sequential Logic Design
Process Control
Flaxer Eli - Process Control
Ch 2 - 1
Logic Devices
●
Logic devices divide into two major types:
●
Combinational Logic
– Current output depends on current input only
– Gates, decoders, multiplexers, ALUs
●
Sequential Logic
– Current output depends on past inputs as well as current input
– Thus has a memory (usually called the state)
– Latches, flip-flops, state machines, counters, shift registers
Flaxer Eli - Process Control
Ch 2 - 2
Sequential Logic Definitions
●
Clock - the master timing element behind the state changes of
most sequential circuits.
– a clock signal is active high if the state changes occur at the rising edge
– and active low if state changes occur at the falling edge.
●
●
●
Clock Period - time between successive transitions in the
same direction.
Clock Frequency - reciprocal of the clock period.
Duty Cycle - the percentage of time that a clock is at its
assertion level.
Flaxer Eli - Process Control
Ch 2 - 3
Clock Characteristics
State change
Active
High
tL
Frequency
= 1/Period
tH
Period
Duty Cycle
= tH/Period
State change
Active
Low
Flaxer Eli - Process Control
tL
Period
tH
Duty Cycle
= tL/Period
Ch 2 - 4
What Are Latches and Flip-flops?
●
Common feedback sequential circuits
●
Latch
– Single-bit storage (memory)
– Changes state at any time due to input change
●
Flip-flop
– Also single-bit storage
– Changes state ONLY when a clock edge or pulse is applied
Flaxer Eli - Process Control
Ch 2 - 5
Types of Latches and Flip-flops
●
Latches
– S-R Latch
– S-R Latch with Enable
– D Latch
●
Flip-flops
–
–
–
–
Edge-Triggered D Flip-Flop
Edge-Triggered S-R Flip-Flop
Edge-Triggered J-K Flip-Flop
T Flip-Flop
Flaxer Eli - Process Control
Ch 2 - 6
S-R Latch
Function Table
Symbol
Set
S
Q
Qa
Reset
R
Q
/Qa
Hold
S
0
R
0
Q
/Q
Reset
0
1
0
1
Set
1
0
1
0
ILLEGAL
1
1
0
0
Last Q Last /Q
Schematic
R
Q
Consider:
Timing Diagram
Propagation delay
Minimum pulse width
Oscillation
/Q
S
Flaxer Eli - Process Control
Ch 2 - 7
D Flip-Flop
D
C
D
C
S
C
R
D
Q
Q
C
1
D
0
Q
/Q
0
1
1
1
1
0
0
X
Last Q Last /Q
Q
Q
Store a data bit, not set/reset
“Transparent latch”
No illegal operation problem
Setup and Hold time
Q
C
/Q
Flaxer Eli - Process Control
Ch 2 - 8
Positive-Edge-Triggered D Flip-Flop
D
Q
>CLK
Q
C
D
S
Q
B
R
Q
S
S
Q
R
Q
CLK
0
1
1
1
0
X
0
Last Q Last /Q
X
1
Last Q Last /Q
R
A
Flaxer Eli - Process Control
/Q
0
S
Q
Q
R
Q
Q’
C =0
D
Q
C =1
D = 0
D =1
D =0
D =1
B
0
1
0
1
S
1
1
1
0
R
1
1
0
1
A
1
0
1
0
Q
N .C .
N .C .
0
1
Q’
N .C .
N .C .
1
0
Ch 2 - 9
Negative-Edge-Triggered D Flip-Flop
D
D
Q
>CLK
Q
Flaxer Eli - Process Control
CLK
Q
/Q
0
0
1
1
1
0
X
0
Last Q Last /Q
X
1
Last Q Last /Q
Ch 2 - 10
Edge-Triggered J-K Flip-Flop
J
>CLK
K
Q
Q
J
K
C
X
X
0
Last Q
Last /Q
X
X
1
Last Q
Last /Q
0
0
0
1
0
1
1
0
1
0
1
1
J
K
D
Q
Q
>CLK
Q
/Q
CLK
Q
/Q
Last Q Last /Q
Last /Q Last Q
Flaxer Eli - Process Control
Ch 2 - 11
T (toggle) Flip-Flop
●
●
A T flip-flop changes state on every clock tick.
Possible circuit designs
– T without enable
C
T
D
Q
Q
>CLK
Q
/Q
CLK
Q
C
/Q
0
Q
/Q
1
/Q
Q
X
0
Q
/Q
X
1
Q
/Q
Flaxer Eli - Process Control
1
J
>CLK
K
Q
Q
Q
/Q
T with enable
T
C
J
>CLK
K
Q
Q
Q
/Q
Ch 2 - 12
Flip-Flop
D F.F.
SR F.F.
D
Q
>CLK
Q
T F.F.
Q
Q
JK F.F.
T
Q
>CLK
Q
Flaxer Eli - Process Control
S
>CLK
R
J
>CLK
K
Q
Q
Ch 2 - 13