DIGITAL TECHNICS
5. LECTURE
Dr. Bálint Pdör
1. Sequential logic, basic principles
Óbuda University,
Microelectronics and Technology Institute
2. Synchronous and asynchronous logic circuits
3. Flip-flops
5. LECTURE
(SEQUENTIAL CIRCUITS AND FLIP-FLOPS)
1
2nd (Spring) term 2010/2011
2
FINITE STATE MACHINE
SEQUENTIAL LOGIC
• The combinational logic circuits we have been studying
so far have no memory. The outputs always follow the
inputs.
• There is an other group of circuits with a memory, which
behave differently depending upon their previous state.
• An example is the vending machine, which must
remember how many and what kinds of coins have been
inserted, and which behave according to not only the
current coin inserted, but also upon how many and what
kind of coins have been deposited previously.
• These are referred to as finite state machines, because
they can have at most a finite number of states.
•
A description of a system with the following components:
1.
2.
3.
4.
5.
A finite number of states
A finite number of external inputs
A finite number of external outputs
An explicit specification of all state transitions
An explicit specification of what determines each
external output value
•
Often described by a state diagram.
– Inputs trigger state transitions.
– Outputs are associated with each state (or with each
transition).
3
4
IMPLEMENTING A FINITE STATE
MACHINE
• Combinational logic
– Determine outputs and next state.
• Storage elements
– Maintain state representation.
SEQUENTIAL CIRCUIT CONCEPTS
The addition of a memory device to a combinational circuit
allows the output to be fed back into the input:
State Machine
Inputs
Clock
Outputs
Combinational
Logic Circuit
Storage
Elements
Input(s)
circuit
Output(s)
memory
5
6
Synchronous and Asynchronous
Input(s)
circuit
Output(s)
memory
Clock
pulse
With synchronous circuits a clock pulse is used to regulate
the feedback, input signal only enabled when clock pulse is
high – acts like a “gate” being opened.
7
A NOR GATE WITH A LUMPED DELAY
ASYNCHRONOUS SEQUENTIAL CIRCUIT
Secondary
variables
Combinational
network with
no delay
This delay between input and output is at the basis of the
functioning of an important memory (storage) element, the
flip-flop.
9
SYNCHRONOUS SEQUENTIAL CIRCUIT
Secondary
excitations
10
CLOCKS
A sequential circuit uses past inputs to determine present
outputs: event ordering.
Clock: circuit emitting a series of pulses with precise pulse
width and repetition rate.
Synchronous sequential circuit: uses clock to decide when
to update the state of the circuit.
Combinational
circuit
Clock
Storage
circuits
11
Most sequential circuits are edge triggered: they change
their state on either rising or the falling edge of
12the pulse.
MEALY AND MOORE MACHINES
There are two types of finite state machines that can be built
from sequential logic circuits:
Moore machine: the output depends only on the internal
state. (since the internal state only changes on a clock
edge, the output also changes on a clock edge).
Mealy machine: the output depends not only on the internal
state, but also on the inputs.
13
EXAMPLE: BLINKING TRAFFIC SIGN
• A blinking traffic sign
– No lights on
– 1 & 2 on
– 1, 2, 3, & 4 on
– 1, 2, 3, 4, & 5 on
– (repeat as long as switch
is turned on)
3
4
1
5
Switch on
2
Switch off
DANGER
MOVE
RIGHT
State bit S1
15
Light 5
S1 S0
Z
Y
X
16
TRAFFIC SIGN LOGIC
Switch
S1
In
S1 S0
S0
0
X
X
0
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
Whenever In=0, next state is 00.
Z = S1+S0, Y = S1, X = S1S0,
D-flip-flop
Outputs
Next State: S1’S0’
(depend on state and input)
Lights 1 and 2
Lights 3 and 4
State bit S0
Transition on each clock cycle.
TRAFFIC SIGN TRUTH TABLES
Outputs
(depend only on state: S1S0)
TRAFFIC SIGN STATE DIAGRAM
D1 =S1ÅS0,
17
Master-slave
flipflop
__
D0 = S0
Z = S1+S0, Y = S1,
X = S1S0,
D1 =S1ÅS0,
18
__
D0 = S0
FLIP-FLOPS
FLIP-FLOPS
Flip-flop, latch or bistable multivibrator
is an electronic circuit which has two stable states. It is
capable to function as a memory.
The most important flip-flops are the following:
R-S (or S-R) flip-flop
J-K flip-flop
T flip-flop
D-G flip-flop
D flip-flop
A flip-flop is controlled by one or two control signals and/or a
gate or clock signal. The output often includes the
complement as well as the normal output.
Sometimes they have separate auxiliary clear and
load/set/preset inputs too.
19
All flip-flops listed above can function in synchronous or
clocked mode, the R-S and D flip-flops can operate in
asynchronous mode too.
The behaviour of a particular type can be described by
truth/characteristic table and the characteristic equation,
which gives the next output in terms of the input control
20
signals and the current output.
SUMMARY OF FLIP-FLOP TYPES
STATE TRANSITION DIAGRAMS
21
NOTES ON HISTORY
The first electronic flip-flop (bistable circuit) was invented in
1919 by W. Eccles and F. W. Jordan (Eccles-Jordan trigger
circuit), and consisted of two active elements (radio-tubes).
The name flip-flop was later derived from the sound
produced on a speaker connected with one of the
backcoupled amplifiers output during the trigger process
within the circuit.
23
22
22
_
THE
RS Q Q
L L no change
L H H L
H L L H
H H L L
Q
BASIC RS FLIP-FLOP
+Ucc
•
•
T1
•
R
T2
•
S
24
_
Q
THE SET-RESET FLIP-FLOP
_
RS Q Q
L
L
H
H
L no change
H H L
L L H
H L L undefined!
NOR gates are controlled by HIGH levels on the input!
25
SOME TYPICAL USES OF FLIP-FLOPS
• A single flip-flop can be used to store one bit.
Static RAMs are built of flip-flops.
• Any one of the flip-flops can be used to build any of the
of the other types.
• A further use to build finite state machines. The flip-flops
remember the machine`s previous state, and digital logic
uses that state to calculate the next state.
• The flip-flops are used to construct various types of
counters.
• Frequency division: a chain of T flip-flops will also
function to divide an input frequency by 2n, where n is
the number of flip-flops in the chain.
27
RS FLIP-FLOP:
IMPLEMENTATION WITH NOR GATES
_____
_
Q=R+Q
CMOS STATIC RS FLIP-FLOP
N- and p-channel
MOSFET pair, both
gates driven
simultaneously :
CMOS inverter
Set and Reset: with pull-down transistors. Flipping occurs by
”brute force”, e.g. by activating RESET, C is discharged through
T1 while the upper pMOS simultaneously pulls it up by charging.
Using a sufficiently large current T1, the circuit will flip, however
the power dissipation and the time delay are relatively large.
26
THE SR FLIP-FLOP OR LATCH
The SR (set/reset) flip-flop is one of the simplest flip/flops
used in digital systems. It can be realized/implemented by
direct feedback of a combinational circuit, i.e. with
asynchronous sequential circuit.
Characteristic equation (derived from the
truth/characteristic table):
_
_
Qn+1 = S + R Qn = R (S + Qn)
and
RS = 0
28
THE S-R (SET-RESET) FLIP-FLOP:
TIMING BEHAVIOUR
_ _____
Q=S+Q
Q is the output of the R gate !
(not allowed)
29
The S-R flip-flop is an active high (positive logic) device.
30
RS FLIP-FLOP:
IMPLEMENTATION WITH NAND GATES
(not allowed)
Q is the output of the S gate !
___
__
Q=SQ
___
_
Q=RQ
31
INSTABILITY
SR FLIP-FLOP
Inverse RS flip-flops can become unstable if both R and
S are set to zero.
All sequential elements are fundamentally unstable
under certain conditions
Invalid transitions
Transitions too close together
Transitions at the wrong time
The problem of logically undefined state (S = R =1) can be
handled by using an additional inverter to generate Q` from
Q (for NAND gate realization):
Q
S
Q
1
_
Q
R
Always consult the relevant data sheets
33
CLOCKED S-R FLIP-FLOP
The clock signal, CLK, turns on the inputs to the flip-flop.
35
For the excitation SR =1 the output will be Q = 1, i.e. the S
input has the priority.
34
TIME DIAGRAM OF RS FLIP-LOP
(NOR GATES)
36
D FLIP-FLOP: CHARACTERISTICS
THE CLOCKED D (DATA) FlLIP-FLOP
D flip-flop
Clocked D flip-flop
Avoids the instability of the RS flip-flop
Retains its last input value
Formally known as a “Delay” flip-flop (”Data” flip-flop)
May become unstable if transitions are too close together
Is generally implemented as a special circuit, not as
pictured here.
39
CLOCKED D FLIP-FLOP
CHARACTERSTICS
The clocked D flip-flop, sometimes called a latch, has a
potential problem: If D changes while the clock is high, the
output will also change. The Master-Slave flip-flop solves this
problem.
40
CLOCKED CMOS D FLIP-FLOP
• Synchronizes transitions with a clock
• Input should remain stable while clock is active
• Transition at the wrong time can cause instability
– Changes while clock is active
– Changes simultaneous with clock
41
42
GATED D FLIP-FLOP
G
Qn+1
Qn
0
0
1
0
1
1
1
0
G
The inputs to the latches/FFs we have seen so far are
controlled by the level of the clock: level-sensitive FFs.
D
It is possible to construct FFs that are edge triggered:
The output changes only at the point of time when the
clock changes from one to the other.
D
_
The third term is necessary for the
Qn+1 = D G + G Qn + D Qn elimination of (static) race hazards.
In each column there is at least one stable state, so the D FF can
be operated asynchronously too.
43
EDGE-TRIGGERED D FLIP-FLOP
Logic structure of edge-triggered D flip-flop (logic diagram of
type 7474).
Auxiliary circuitry: asynchronous CLEAR and PRESET
45
MASTER-SLAVE FLIP-FLOP
• A pair of gated D-latches,
to isolate next state from current state.
During 1st phase (clock=1),
previously-computed state
becomes current state and is
sent to the logic circuit.
EDGE-TRIGGERED FLIP-FLOP
During 2nd phase (clock=0),
next state, computed by
logic circuit, is stored in
Latch A.
47
Circuits are called edge-triggered.
44
THE MASTER-SLAVE FLIP-FLOP
The rising edge of the clock clocks new data into the Master,
while the Slave holds previous data. The falling edge clocks
the new Master data into the Slave.
46
MASTER-SLAVE D FLIP-FLOP:
LOGIC DIAGRAM
Auxiliary circuitry: asynchronous CLEAR and PRESET
48
J-K FLIP-FLOP: STATE TRANSITION
TABLE AND DIAGRAM
JK FLIP-FLOP
The JK flip-flop augments the behaviour of the SR flip-flop
by interpreting the S = R = 1 conditions as a ”flip”
(”toggle”) command:
JK
Qn
0
J K Qnext Comment
0 0 Qprev hold state
0 1 0
reset
1 0 1
set
_
1 1 Qprev toggle
1
49
GATED/CLOCKED JK FLIP-FLOP
J
Qn+1
JK
00 01 11 10
00,01
00,10
—————————
0
0
1
1
10,11
—————————
0
1
1
0
0
1
—————————
01,11
There is no stable state in the J= K=1 column, therefore the
JK flip-flop can only be realized on the form of synchronous
sequential (i.e. clocked) circuit.
50
TIME DIAGRAM OF J-K FLIP-FLOP
·
G
K
·
_
_
Qn+1 = J Qn + K Qn
53
54
54
T-FLIP-PLOP
T flip-flops do not really exist (!), constructed from JK or D
FFs.
Usually best choice for implementing counters.
To create a T-FF using a D flip-flop.
Add a feedback connection that makes the input signal D
equal either the value of Q or Q’ under the control of the
signal T.
56
CHARACTERISTIC EQUATIONS
OF FLIP-FLOPS: A SUMMARY
T FLIP-FLOP BUILT WITH
A D FLIP-FLOP
_
_
D = T Qn + T Qn
&
T
1
D
CLK
&
T
_
Qn+1 = S + R Qn
_
_
_
Qn+1 = J Qn + K Qn + J K
_
_
Qn+1 = T Qn + T Qn = T Å Qn
D
Qn+1 = Dn
D-G
_
Qn+1 = D G +G Qn + D Qn
RS
JK
Q
_
Q
Clock
Note that T flip-flops are not available in the CMOS and TTL
logic families. D flip-flops are available in PLDs.
57
Note: The third terms in the equation of JK and D-G flip-flops
serve for the elimination of race hazards
58
EXCITATION TABLES OF FLIP-FLOPS
QnQn+1
R
S
J
K
D
T
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
0
0
x
0
0
X
0
0
0
1
0
1
1
X
1
1
1
0
1
0
X
1
0
1
1
1
0
X
X
0
1
0
The excitation table lists the required inputs for a given change
of state, i.e. the input conditions that will cause the transition
form a given present state to the next state.
The excitation table is required and is used in the design
process.
59
CONVERSION OF FLIP-FLOPS
Combinational circuit
X
CC
implementing flip-flop
y
Z
FF
y
Flip-flop to be implemented
Clock
Each flip-flop type can be realized and implemented on the
60
basis of any other type.
EXAMPLE: IMPLEMENTATION OF JK
FLIP-FLOP WITH D FLIP-FLOP
SUMMARY OF FLIP-FLOP TYPES
S=R=1 not
allowed
J
&
1
K
D
CLK
&
Q
_
Q
Most versatile
type
•
•
Most simple
Gated (DG)
Copies input to
output
Clock
Note that D flip-flops are available in some PLA circuits.
61
IMPLEMENTATION OF FLIP-FLOPS:
SOME PRACTCAL ASPECTS
Complements
output if activated
62
APPLICATION OF FLIP-FLOPS: SOME
PRACTICAL ASPECTS
• In the popular CMOS and TTL logic families T flip-flop is
not available. It should be build on the basis of an other
type of flip-flop.
• T flip-flops are well suited for straightforward binary
counters.
But may yield worst gate and pin counts.
• TTL, CMOS: basically JK and D flip-flops.
• No reason to choose RS over JK FFs: it is a proper subset
of JK. RS FFs don’t exist anyway.
Tend to yield best choice for packaged logic where gate
count is the key.
• PLA, PLD: only D flip-flop (!), the JK flip-flop should be
implemented by additional circuitry.
• RS flip-flop: in TTL it is based on NAND gates, in CMOS
it is based on NOR gates.
63
SUMMARY OF SOME ASPECTS
OF FLIP-FLOPS
Development of D flip-flop
Level-sensitive is used in custom ICs
Edge-triggered uesd in programmable logic deices
Good choice for data storage register
Historically JK flip-flop was popular but noe never used
Similar to RS but wit 11 used to toggle output
Good in days of TTL/SSI (more complex input function)
Not a good choice for PALs/PLAs as it requires two inputs
Can always be implemented using D flip-flops
Preset and clear inputs are highly desirable on flip-flops
Used at start-up or to reset systems to a known state
65
• D FFs yield simplest design procedure. In many cases
give the best pin count.
D storage devices are very transistor efficient in VLSI.
Best choice where area/pin count is the key.
64
SUMMARY OF SOME ASPECTS
OF FLIP-FLOPS
RS clocked latch:
Used as storage element in narrow width clocked systems
Its use is not recommended!
However fundamental building block of other flip-flop types
JK flip-flop:
Versatile building block
Can be used to implement D and T flip-flops
Usually requires least amount of logic to implement f(In, Q)
But has two inputs with increase wiring complexity
D flip-flops:
Minimizes wires, much preferred in VLSI technologies
Simplest design technique
Best choice for storage registers
T flip-flops:
Don’t really exist, constructed from JK flip-flops
Usually best choice for implementing counters
66