A
B
C
D
E
1
1
PWWAA
LC Marseille
2
2
LA-6842P REV 0.2 Schematic
Intel Processor(ARD) /PCH(HM55)
2010-07-22 Rev 0.2
3
3
4
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Cover Page
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
E
1
of
45
A
B
C
Compal Confidential
D
Fan Control
APL5607
Intel Arrandale
Model Name : PWWAA
File Name : LA-6842P
E
Clock Generator
RTM890N-631-GRT
page 6
page 13
1
1
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
rPGA-988
Dual Channel
page 5,6,7,8,9,10
BANK 0, 1, 2, 3
page 11,12
1.5V DDRIII 800/1066 MT/s
USB
FDI X8
USB port 0,1
DMI X4
2.7GHz
page 25
2.5GHz
RTS5137
USB port 10
2IN1
LCD Conn.
page 13
page 26
USB
Int. Camera
USB port 11
page 13
5V 480MHz
CRT
2
page 14
USB
USB port 13
page 27
5V 480MHz
PCIeMini Card
WLAN
PCIe 1x
1.5V 2.5GHz(250MB/s)
PCIe port 1
page 27
Intel Ibex Peak
SATA port 1
5V 3GHz(300MB/s)
RJ45
RTL8105E-GR 10/100M
page 28
PCIe port 0
PCIe 1x
page 28
SATA port 4
BGA-951
1.5V 2.5GHz(250MB/s)
2
PCIeMini Card
WiMax
5V 3GHz(300MB/s)
SATA HDD0
page 25
SATA ODD
page 25
PCI
3
3
Power/B conn.
page 32
3.3V 33 MHz
LPC BUS
page 16~24
HD Audio
3.3V/1.5V 24MHz
RTC CKT.
HDA Codec
page 16
SPI ROM
page 16
Debug Port
ALC259-GR
ENE KB926 E0
page 32
page 29
page 31
DC/DC Interface CKT.
page 34
Touch Pad
page 33
Power Circuit DC/DC
Int.
MIC CONN
(LVDS CONN)
page 13
EC ROM
Int.KBD
page 32
page 32
Ext.
MIC CONN
page 30
HP CONN
page 30
SPK CONN
page 30
4
4
page 35~44
2010/06/21
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Block Diagrams
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
E
2
of
45
5
4
3
2
1
DESIGN CURRENT 0.1A
+3VL
+5VL
DESIGN CURRENT 0.1A
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9
DESIGN CURRENT 5A
+5VALW
DESIGN CURRENT 2A
+1.8VS
DESIGN CURRENT 4A
+5VS
SUSP#
MP2121DQ
SUSP
D
D
N-CHANNEL
SI4800
BCPWON
DESIGN CURRENT 0.5A
P-CHANNEL
AO-3413
KB_LED
RT8205EGQW
+5VS_L_BCAS
DESIGN CURRENT 400mA
+5VS_LED
DESIGN CURRENT 300mA
+3VS_HDP
DESIGN CURRENT 1.6A
+5VS_ODD
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_EN#
P-CHANNEL
AO-3413
DESIGN CURRENT 5A
Ipeak=5A, Imax=3.5A, Iocp min=7.7
+3VALW
WOL_EN#
DESIGN CURRENT 330mA
P-CHANNEL
AO-3413
SUSP
C
+3V_LAN
DESIGN CURRENT 4A
N-CHANNEL
SI4800
C
+3VS
LCD_ENVDD
DESIGN CURRENT 1.5A
P-CHANNEL
AO-3415
BT_PWR#
+LCD_VDD
DESIGN CURRENT 180mA
+BT_VCC
P-CHANNEL
AO-3413
FELICA_PWR
DESIGN CURRENT 0.5A
P-CHANNEL
AO-3413
VR_ON
+FLICA_VCC
DESIGN CURRENT 48A
+CPU_CORE
DESIGN CURRENT 15A
+GFX_CORE
ISL62883HRZ
GFXVR_EN
ADP3211AMNR2G
VTTP_EN
B
B
Ipeak=18A, Imax=12.6A, Iocp min=19.8
APW7138NITRL
DESIGN CURRENT 18A
+VTT
SUSP#
Ipeak=7A, Imax=4.9A, Iocp min=7.7
RT8209BGQW
DESIGN CURRENT 7A
+1.05VS
SUSP#
Ipeak=15A, Imax=10.5A, Iocp min=16.5
RT8209BGQW
DESIGN CURRENT 15A
+1.5V
SUSP
DESIGN CURRENT 2A
N-CHANNEL
+1.5V_CPU
FDS6676AS
SUSP
DESIGN CURRENT 2A
N-CHANNEL
+1.5VS
FDS6676AS
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A
+0.75VS
G2992F1U
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
A
2
Title
Power Tree
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
3
of
45
A
Voltage Rails
B
( O MEANS ON
+RTCVCC
D
E
X MEANS OFF )
+B
+5VL
+5VALW
+3VL
+3VALW
+5VS
+1.5V
+3VS
+VSB
power
plane
1
C
+1.5VS
+VGA_CORE
+CPU_CORE
BTO Option Table
+VTT
Function
+1.05VS
+1.8VS
MINI PCI-E SLOT
LAN
description
SLOT1
explain
WLAN/BT
+1.1VS
State
1
+0.75VS
LAN
10/100M
BTO
Camera & Mic
Function
Camera & Mic
description
2
S0
O
O
O
O
O
O
explain
Camera & Mic
S1
O
O
O
O
O
O
BTO
CAM@
S3
O
O
O
O
O
X
Function
O
O
O
O
X
X
description
S5 S4/AC
S5 S4/ Battery only
O
O
O
X
X
X
S5 S4/AC & Battery
don't exist
O
X
X
X
X
X
2
S3 Power Saving
S3 Power Saving
Power Saving
explain
BTO
PCH SM Bus Address
3
Power
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
Clock Generator
D2 H
1101 0010 b
+3VS
New Card
+3VS
WLAN/WIMAX
+3VS
SIGNAL
3
SLP_S3# SLP_S4# SLP_S5#
Full ON
Clock Generator
EC SM Bus1 Address
4
STATE
EC SM Bus2 Address
Power
Device
HEX
Address
Power
Device
HEX
Address
+3VL
Smart Battery
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
Power
Device
HEX
Address
HIGH
HIGH
HIGH
S1(Power On Suspend)
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Notes List
Size Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
E
4
of
45
5
4
3
2
1
JCPUB
AN26
AK15
2
21 H_THERMTRIP#
PROCHOT#
THERMTRIP#
A18
A17
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
H_PWRGOOD
VCCPW RGOOD_1
AN27
VCCPW RGOOD_0
1
VTTPWROK_CPU AM15
1
TAPPWRGD
SM_DRAMPW ROK
VTTPW RGOOD
AM26
TAPPW RGOOD
AL14
RSTIN#
BUF_PLT_RST#_R
1.5K_0402_1%
2
20 BUF_PLT_RST#
AN14
DRAMPWROK AK13
18 DRAMPWROK
39 VTTPWROK_CPU
750_0402_1%
R29
PM_SYNC
R30
R31
750_0402_1%
JTAG & BPM
2
21 H_PWRGOOD
DRAMPWROK
AL15
2
1 10K_0402_5%
2
1 10K_0402_5%
AL1 SM_RCOMP_0
AM1 SM_RCOMP_1
AN1 SM_RCOMP_2
R6 1
R7 1
R8 1
AN15 PM_EXTTS#0
AP15 PM_EXTTS#_R
PRDY#
PREQ#
AT28
AP27
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AN28
AP28
AT27
XDP_TCK
XDP_TMS
XDP_TRST#
TDI
TDO
TDI_M
TDO_M
AT29
AR27
AR29
AP29
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
DBR#
AN25
XDP_DBRESET#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
2
R12
2 100_0402_1%
2 24.9_0402_1%
2 130_0402_1%
1
0_0402_5%
DDR3 Compensation Signals
Layout Note:Please these
resistors near Processor
R19 unmount for NPS@
@
PM_EXTTS# 11,12
2
R19
SM_DRAMRST#_CPU
IC,AUB_CFD_rPGA,R0P9
@
1
0_0402_5%
3
Routed as a single daisy chain
R127
100K_0402_5%
2
R312
1
1K_0402_5%
1
C
Add on 10/28
XDP_TDI_R
1
R20
2
0_0402_5%
XDP_TDI
Scan Chain
(Default)
STUFF -> R20, R23, R27
NO STUFF -> R21, R26
XDP_TDO_M
1 @
R21
2
0_0402_5%
XDP_TDO
CPU Only
STUFF -> R20, R21
NO STUFF -> R23, R26, R27
GMCH Only
STUFF -> R26, R27
NO STUFF -> R20, R21, R23
1 @
R26
2
0_0402_5%
1
R27
2
0_0402_5%
R23
0_0402_5%
XDP_TDO_R
@
XDP_PRDY#
R358 1
XDP_PREQ#
R359 1
XDP_TCK
R360 1
XDP_TMS
R367 1
C301, Q41,
R127 from PS@
to mount
C301
0.047U_0402_16V7K
XDP_DBRESET# 18
XDP_TDI_M
For S3 CPU Power Saving
SM_DRAMRST# 11,12
Q41
BSS138_NL_SOT23-3
RST_GATE 21
+3VS
JTAG MAPPING
R28 unmount for NPS@
R29 always mount for PS@
B
XDPSFF-24Pin
Connector
2 0_0402_5% XDP_PRDY#_R
@
2 0_0402_5% XDP_PREQ#_R
@
place near JCPU
XDP_PREQ#_R
XDP_PRDY#_R
DRAMPWROK
IN1
2
IN2
0715 --> change BOM structure to mount
R370 1
XDP_BPM#0
R371 1
2 0_0402_5% XDP_BPM#0_R
XDP_BPM#2_R
XDP_BPM#3_R
@
XDP_BPM#1
U16
2 0_0402_5% XDP_BPM#1_R
R373 1
4
R33
DRAMPWROK
1.5K_0402_1%
XDP_BPM#2
@
XDP_BPM#3
@
XDP_DBRESET# R390 1
1K_0402_5%
2
2
0_0402_5%
2 0_0402_5% XDP_BPM#3_R
R375 1
SN74AHC1G08DCKR_SC70-5
1
R84
2 0_0402_5% XDP_BPM#2_R
R374 1
@ R32
1
1
@ R35
H_PWRGOOD
TAPPWRGD
@
O
@
2
0_0402_5%
2 0_0402_5% XDP_TRST#_R
@
2 0_0402_5% XDP_DBRESET#_R
+VTT
EMI request, close to JCPU
H_PWRGOOD_R
TAPPWRGD_R
CLK_CPU_XDP
CLK_CPU_XDP#
XDP_RST#_R
XDP_DBRESET#_R
1
2
51_0402_5%
C1
0.1U_0402_10V6K
@ 2
1
1
XDP_TRST#
P
34,39 VTTPWROK
VTTPWROK
2
0.1U_0402_16V4Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
XDP_BPM#0_R
XDP_BPM#1_R
XDP_TDO
XDP_TRST#_R
XDP_TDI
XDP_TMS_R
2
5
1
C163
1 C488 VTTPWROK_CPU
2 0_0402_5% XDP_TMS_R
@
G
1000P_0402_50V7K 2
1 C487
3
1000P_0402_50V7K 2
XDP_TCK_R
1
R14
R11
51_0402_5%
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
25
26
A
MOLEX_52435-2472
@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
2010/06/21
2011/06/21
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
B
JXDP
2 0_0402_5% XDP_TCK_R
@
+3VALW
D
SM_DRAMRST#_CPU
F6
1
1 H_PWRGOOD1_R
R25
2
0_0402_5%
R28 @
1.1K_0402_1%
RESET_OBS#
PMSYNCH
+1.5V_CPU
C
AP26
PWR MANAGEMENT
18
H_CPURST#
2
1K_0402_5%
1
R36
R15
PM_EXTTS#_R R13
G
XDP_RST#_R
PM_EXTTS#0
D
H_CPURST#
+VTT
S
R10
68_0402_5%
@
CLK_PEG 17
CLK_PEG# 17
Unused by Clarksfield rPGA989
2
+VTT
+VTT
H_PROCHOT#_D
2
68_0402_5%
1
R9
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
2
Power has removed VR_TT#
E16
D16
1
PECI
PEG_CLK
PEG_CLK#
CLK_CPU_BCLK 21
CLK_CPU_BCLK# 21
CLK_CPU_XDP_R 1
CLK_CPU_XDP
2
CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP#
R42 @
0_0402_5%
1
AT15
PECI
CATERR#
AR30
AT30
2
AK14
BCLK_ITP
BCLK_ITP#
1
21
CATERR#
2
49.9_0402_1%
SKTOCC#
THERMAL
1
R18
COMP0
A16
B16
2
D
AH24
COMP1
BCLK
BCLK#
CLOCKS
TP_SKTOCC#
T41
COMP2
DDR3
MISC
PAD
+VTT
COMP3
MISC
H_COMP3 AT23
2
20_0402_1%
H_COMP2 AT24
2
20_0402_1%
H_COMP1 G16
2
49.9_0402_1%
H_COMP0 AT26
2
49.9_0402_1%
1
R1
1
R2
1
R4
1
R3
2
Title
CPU CLK/MISC/JTAG
Size Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
5
of
45
5
4
3
2
1
D
D
JCPUA
A24
C23
B22
A21
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
18
18
18
18
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B24
D23
B23
A22
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
18
18
18
18
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
D24
G24
F23
H23
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
18
18
18
18
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
D25
F24
E23
G23
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
E22
D21
D19
D18
G21
E19
F21
G18
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
18
18
18
18
18
18
18
18
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
D22
C21
D20
C18
G22
E20
F20
G19
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
18 FDI_FSYNC0
18 FDI_FSYNC1
F17
E17
FDI_FSYNC[0]
FDI_FSYNC[1]
18 FDI_INT
C17
FDI_INT
18 FDI_LSYNC0
18 FDI_LSYNC1
F18
D17
FDI_LSYNC[0]
FDI_LSYNC[1]
Intel(R) FDI
18
18
18
18
18
18
18
18
B
PCI EXPRESS -- GRAPHICS
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
DMI
C
18
18
18
18
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
B26
A26
B27
A25
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_COMP 1
R38
2
49.9_0402_1%
PEG_RBIAS 1
R39
2
750_0402_1%
C
FAN Control Circuit
+5VS
1A
2
C3
10U_0805_10V4Z
JFAN @
+FAN1
1
2
U1
1
2
3
4
+FAN1
31
EN_DFAN1
10mil
1
2
EN
VIN
VOUT
VSET
GND
GND
GND
GND
C4
@ 1000P_0402_25V8J
1
8
7
6
5
1
2
3
1
2
3
4
5
GND
GND
B
ACES_85204-0300N
APL5607KI-TRG_SO8
C5
10U_0805_10V4Z
R34
10K_0402_5%
1
+3VS
2
FAN_SPEED1 31
C6
0.01U_0402_25V7K
IC,AUB_CFD_rPGA,R0P9
@
Remove Cap, for EMI
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
CPU DMI/FDI/PEG
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
6
of
45
5
4
3
2
JCPUC
JCPUD
12 DDR_B_D[0..63]
D
C
B
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AC3
AB2
U7
SA_BS[0]
SA_BS[1]
SA_BS[2]
11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_W E#
AE1
AB3
AE9
SA_CAS#
SA_RAS#
SA_WE#
AA6
AA7
P7
DDRA_CLK0 11
DDRA_CLK0# 11
DDRA_CKE0 11
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
Y6
Y5
P6
DDRA_CLK1 11
DDRA_CLK1# 11
DDRA_CKE1 11
SA_CS#[0]
SA_CS#[1]
AE2
AE8
DDRA_SCS0# 11
DDRA_SCS1# 11
SA_ODT[0]
SA_ODT[1]
AD8
AF9
DDRA_ODT0 11
DDRA_ODT1 11
DDR_A_DM[0..7]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
B9
D7
H7
M7
AG6
AM7
AN10
AN13
11
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
C9
F8
J9
N9
AH7
AK9
AP11
AT13
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
C8
F9
H9
M9
AH8
AK10
AN11
AR13
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
11
11
11
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AB1
W5
R7
SB_BS[0]
SB_BS[1]
SB_BS[2]
12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_W E#
AC5
Y7
AC6
SB_CAS#
SB_RAS#
SB_WE#
12
12
12
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
W8
W9
M3
DDRB_CLK0 12
DDRB_CLK0# 12
DDRB_CKE0 12
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
V7
V6
M2
DDRB_CLK1 12
DDRB_CLK1# 12
DDRB_CKE1 12
SB_CS#[0]
SB_CS#[1]
AB8
AD6
DDRB_SCS0# 12
DDRB_SCS1# 12
SB_ODT[0]
SB_ODT[1]
AC7
AD1
DDRB_ODT0 12
DDRB_ODT1 12
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
D4
E1
H3
K1
AH1
AL2
AR4
AT8
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D5
F4
J4
L4
AH2
AL4
AR5
AR8
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C5
E3
H4
M5
AG2
AL5
AP5
AR7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DM[0..7]
D
12
C
DDR SYSTEM MEMORY - B
11 DDR_A_D[0..63]
11
11
11
1
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
12
12
B
DDR_B_MA[0..15]
12
IC,AUB_CFD_rPGA,R0P9
@
A
A
IC,AUB_CFD_rPGA,R0P9
@
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
CPU DDRIII
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
7
of
45
5
4
A
(Place these capacitors under CPU socket Edge, top layer)
(Place these capacitors between inductor and socket on Bottom)
+VTT
+CPU_CORE
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
D
C144 1
C267 1
+
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
2 390U_2.5V_M_R10
C81 1
2 10U_0805_10V4K
+
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
2 390U_2.5V_M_R10
C83 1
2 10U_0805_10V4K
C85 1
2 10U_0805_10V4K
1
2
1
C71
2
10U_0805_10V4K
C87 1
2 10U_0805_10V4K
C89 1
2 22U_0805_6.3V6M
C88 1
2 10U_0805_10V4K
C91 1
2 22U_0805_6.3V6M
C90 1
2 10U_0805_10V4K
C92 1
2 10U_0805_10V4K
C94 1
2 10U_0805_10V4K@
SF000002O00
ESR 10m-ohm
H6.3
1
C72
2
1
C73
2
10U_0805_10V4K
1
C74
2
1
C75
2
10U_0805_10V4K
1
C76
2
1
C77
2
10U_0805_10V4K
1
C78
2
C79
10U_0805_10V4K
(Place these capacitors under CPU socket, top layer)
+CPU_CORE
10U_0805_10V4K
1
2
Power team request for F-Din
10U_0805_10V4K
1
C98
2
10U_0805_10V4K
1
C99
2
10U_0805_10V4K
1
C100
2
10U_0805_10V4K
1
C101
2
1
C102
2
10U_0805_10V4K
1
C103
C104
2
10U_0805_10V4K
(Place these capacitors on CPU cavity, Bottom Layer)
C
+CPU_CORE
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
C114
1
C179
1
C131
22U_0805_6.3V6M
1
C116
1
C132
2
2
2
C129
1
C149
C105
1
1
C106
2
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C107
2
C108
2
1
22U_0805_6.3V6M
C109
2
1
C110
2
1
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C111
1
C112
2
PSI#
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
VTT_SELECT
AN33
H_PSI#
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34 H_DPRSLPVR_R 1
R62
CPU_VID0 42
CPU_VID1 42
CPU_VID2 42
CPU_VID3 42
CPU_VID4 42
CPU_VID5 42
CPU_VID6 42
H_DPRSLPVR 42
G15
2
0_0402_5%
H_VTTSELECT
T3
CRB default setting:
VID[6:0]=[0100111]
42
1
C113
VCC_SENSE
VSS_SENSE
AN35
AJ34
AJ35
2
1
22U_0805_6.3V6M
C115
2
1
C148
2
1
2
22U_0805_6.3V6M
B
VTT Rail
TOP side (under inductor)
Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V
+CPU_CORE
PAD
H_VTTSELECT = low, 1.1V
C121
1
330U_D2_2.5VM_R9M
1
1
+
C122
+
+
2
C123
330U_D2_2.5VM_R9M
1
C124
330U_D2_2.5VM_R9M
2
+
2
IMVP_IMON 42
VCCSENSE_R R65
VSSSENSE_R R66
1
1
2 0_0402_5%
2 0_0402_5%
1
R64
VCCSENSE
VSSSENSE
1
VTT_SENSE
VSS_SENSE_VTT
C130
22U_0805_6.3V6M
330U_D2_2.5VM_R9M
2
ISENSE
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
H_VTTSELECT = high, 1.05V
B15
A15
VTT_SENSE 39
VSS_SENSE_VTT 39
R67
2
100_0402_1%
+CPU_CORE
Check list:
VCCSENSE 42
VSSSENSE 42
+CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
2
100_0402_1%
+VTT: 4x 330uF, 7x 22uF, 8x 10uF
near CPU
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
IC,AUB_CFD_rPGA,R0P9
@
5
1
+CPU_CORE
POWER
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
1.1V RAIL POWER
Auburndale:18A
CPU CORE SUPPLY
B
Clarksfield: 21A
Auburndale:48A
CPU VIDS
C
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
Clarksfield: 65A
SENSE LINES
D
2
Material Note (+VTT):
390uF/ 10mohm, number are 3,
power x1, HW x2
JCPUF
+CPU_CORE
3
2010/06/21
2011/06/21
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Title
CPU POWER-1
Size Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
8
of
45
5
4
3
2
1
+1.5V_CPU
+1.5V_CPU
1
2
3
4
C273
form PS@ to mount
FDS6676AS_SO8
1
SUSP
5
4
2N7002DW -T/R7_SOT363-6
2
R417
820K_0402_5%
+VSB
Q46A
2
1
Q46B
7/22 modified for cost down.
R418
1
2
220K_0402_5%
10U_0805_10V4K
1
2
6
1
JUMP_43X79
47P_0402_50V8J
D
D
D
D
8
7
6
5
2
1
1
0.1U_0402_25V6
2
R424
470_0805_5%
1
@
S
S
S
G
3
1
C93
@
PJ32
2
1
C119
@
2
+1.5VS
C472
47P_0402_50V8J
47P_0402_50V8J
2
1
C118
@
2
2
1
47P_0402_50V8J
C97
@
Q33
3A
+GFX_CORE
D
+1.5V
EMI request
2
For
D
SUSP
SUSP
34,41
2N7002DW -T/R7_SOT363-6
Change C271 to 4.5mm height OS-CON at PVT
+GFX_CORE
JCPUG
C95
2
C127
2
22U_0805_6.3V6M
1
2
C117
1
C96
2
1U_0402_6.3V4Z
1
1
C120
2
C86
10U_0805_6.3V6M
2
10U_0805_6.3V6M
+GFX_CORE
C
@
C496 +
330U_D2_2VM_R6M
1
2
For POLY Cap.
0714 --> C271 mount,
C496 unmount
22U_0805_6.3V6M
Auburndale:3A
1
1
2
2
C142
J24
J23
H25
VTT1_45
VTT1_46
VTT1_47
FDI
B
Clarksfield: 5A
Auburndale:22A
+VTT
C141
GRAPHICS
Add C496 Co-Layout with C271
VAXG_SENSE
VSSAXG_SENSE
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
AT25
AM24
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6
22U_0805_6.3V6M
(Place these capacitors under CPU socket, top layer)
VTT0_59
VTT0_60
VTT0_61
VTT0_62
P10
N10
L10
K10
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
J22
J20
J18
H21
H20
H19
VCCPLL1
VCCPLL2
VCCPLL3
L26
L27
M26
VCC_AXG_SENSE 43
VSS_AXG_SENSE 43
R82
Change R136 to 470
ohm
for GFX issue
1
R50
2
470_0402_5%
C230 1
2 0.1U_0402_16V4Z
C314 1
2 0.1U_0402_16V4Z
C205 1
2 0.1U_0402_16V4Z
C186 1
2 0.1U_0402_16V4Z
C
remove PJ30
+1.5V_CPU
1U_0402_6.3V4Z
1U_0402_6.3V4Z
22U_0805_6.3V6M
2
1
1
C133
1
C134
2
1
C135
2
1U_0402_6.3V4Z
1
C136
1
C137
2
2
1U_0402_6.3V4Z
1
C138
2
1
1U_0402_6.3V4Z
@
2
1
1
+1.5V
+ C216
390U_2.5V_M_R10
C139
2
PJ31
JUMP_43X79
2
PJ31 need to open for
S3 CPU Power Saving
2
22U_0805_6.3V6M
(Place these capacitors under CPU socket Edge, top layer)
1
2
B
C143
10U_0805_10V4K
1
2
C145
22U_0805_6.3V6M
+1.8VS
Clarksfield: 0.6A
+1.8VS_H_PLL 1U_0402_6.3V4Z
C151
1U_0402_6.3V4Z
1
1
2
2
4.7U_0603_6.3V6K
1
C152
2
R71
1
0_0805_5%
1
C153
C154
2
C155
2 22U_0805_6.3V6M
2.2U_0603_6.3V4Z
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2
100_0402_1%
1 1K_0402_5%
@
IC,AUB_CFD_rPGA,R0P9
@
5
1
(Place these capacitors under CPU socket, top layer)
Auburndale:1.35A
A
+GFX_CORE
+VTT
1.1V
2
VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58
2
100_0402_1%
+VTT
1.8V
2
C147
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
PEG & DMI
1
43
43
43
43
43
43
43
GFXVR_EN 43
T8 PAD
GFXVR_IMON 43
GFXVR_DPRSLPVR
GFXVR_IMON
Auburndale:18A
1
1
2 0_0402_5%
2 0_0402_5%
near CPU
R687 2
22U_0805_6.3V6M
+VTT
22U_0805_6.3V6M
R365 1
R384 1
GFXVR_EN
Clarksfield: 21A
C146
VCC_AXG_SENSE_R
VSS_AXG_SENSE_R
AR22
AT22
For Power request
- 1.5V RAILS
2
1
R69
DDR3
1
C271 +
330U_2.5V_M_R17
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
SENSE
LINES
1
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
GRAPHICS VIDs
1U_0402_6.3V4Z
POWER
22U_0805_6.3V6M
3
2
Title
CPU POWER-2
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
9
of
45
4
3
JCPUI
C
B
1
JCPUH
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
NCTF
D
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
2
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
H_NCTF1
H_NCTF2
H_NCTF6
H_NCTF7
PAD T4
PAD T5
PAD T6
PAD T7
IC,AUB_CFD_rPGA,R0P9
@
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUE
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
IC,AUB_CFD_rPGA,R0P9
@
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9 (SA_DIMM_VREF)
RSVD10(SB_DIMM_VREF)
RSVD11
RSVD12
RSVD13
RSVD14
WW41 Recommend not pull down
PCIE2.0 Jitter is over on ES1
3.01K_0402_1% 1 @ R74
2
3.01K_0402_1% 1 @ R75
3.01K_0402_1% 1 @ R76
2
2
CFG0 - PCI-Express Configuration Select
*1:Single PEG
0:Bifurcation enabled
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
B19
A19
RSVD15
RSVD16
A20
B20
RSVD17
RSVD18
U9
T9
RSVD19
RSVD20
AC9
AB9
RSVD21
RSVD22
C1
A3
CFG3 - PCI-Express Static Lane Reversal
*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
RESERVED
5
RSVD32
RSVD33
AJ13
AJ12
RSVD34
RSVD35
AH25
AK26
RSVD36
RSVD_NCTF_37
AL26
AR2
RSVD38
RSVD39
AJ26
AJ27
RSVD_NCTF_40
RSVD_NCTF_41
AP1
AT2
RSVD_NCTF_42
RSVD_NCTF_43
AT3
AR1
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
E15
F15
A2
D15
C15
AJ15
AH15
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
RSVD_NCTF_23
RSVD_NCTF_24
J29
J28
RSVD26
RSVD27
A34
A33
RSVD_NCTF_28
RSVD_NCTF_29
C35
B35
RSVD_NCTF_30
RSVD_NCTF_31
C
B
VSS
CFG4 - Display Port Presence
*1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
D
AP34
IC,AUB_CFD_rPGA,R0P9
@
*:Default
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
CPU GND/RESERVED/XDP
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
10
of
45
4
3
+1.5V
DDR3 SO-DIMM A
Standard Type
JDDRL
DDR_A_D8
DDR_A_D9
D
DDR_A_DQS#1
DDR_A_DQS1
close to JDDRL.1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
7
DDRA_CKE0
C
7
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
7
7
DDRA_CLK0
DDRA_CLK0#
DDR_A_MA10
7
DDR_A_BS0
7
7
DDR_A_W E#
DDR_A_CAS#
DDR_A_MA13
7
DDRA_SCS1#
DDR_A_D32
DDR_A_D33
B
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
1
C182
2
1
2
5
R91
10K_0402_5%
2
1
C181
2.2U_0603_6.3V4Z
+3VS
0.1U_0402_16V4Z
DDR_A_D58
DDR_A_D59
R90 1
2
10K_0402_5%
A
+0.75VS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
+1.5V
7 DDR_A_DQS#[0..7]
1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
M1 Circuit
7 DDR_A_DQS[0..7]
DDR_A_DQS#0
DDR_A_DQS0
7 DDR_A_D[0..63]
+1.5V
R79
1K_0402_1%
7 DDR_A_DM[0..7]
DDR_A_D6
DDR_A_D7
7 DDR_A_MA[0..15]
R83
1K_0402_1%
DDR_A_D12
DDR_A_D13
DDR_A_DM1
2
R78
1
0_0402_5%
+VREF_DQB
2
R80
1
0_0402_5%
+VREF_DQA
+V_DDR3_DIMM_REF
2
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
1
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
D
R81
1K_0402_1%
R83 from PS@ to mount
SM_DRAMRST# 5,12
2
DDR_A_DM0
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
1
1
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
2
2
DDR_A_D0
DDR_A_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDRA_CKE1 7
DDR_A_MA15
DDR_A_MA14
C
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1 7
DDRA_CLK1# 7
DDR_A_BS1 7
DDR_A_RAS# 7
DDRA_SCS0# 7
DDRA_ODT0 7
+V_DDR3_DIMM_REF
DDRA_ODT1 7
R89
1
0_0402_5%
+DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
C161
2.2U_0603_6.3V4Z
1
C157
2.2U_0603_6.3V4Z
C156
0.1U_0402_16V4Z
+VREF_DQA
2
1
2
2
B
Layout Note:
Place near JDDRL
1
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA
Layout Note:
Place near JDDRL1.203 and 204
2
+1.5V
C218 1
+
+1.5V
C162
0.1U_0402_16V4Z
5
2 390U_2.5V_M_R10
close to JDDRL.126
DDR_A_D46
DDR_A_D47
C166 1
2 10U_0805_6.3V6M
C168 1
2 10U_0805_6.3V6M
C171 1
2 10U_0805_6.3V6M
DDR_A_DM6
C174 1
2 10U_0805_6.3V6M
DDR_A_D54
DDR_A_D55
C176 1
2 10U_0805_6.3V6M
C178 1
2 10U_0805_6.3V6M
DDR_A_D52
DDR_A_D53
DDR_A_D60
DDR_A_D61
+1.5V
+0.75VS
C164 1
2 0.1U_0402_16V4Z
C167 1
2 0.1U_0402_16V4Z
C170 1
2 0.1U_0402_16V4Z
C173 1
2 0.1U_0402_16V4Z
C165 1
2 10U_0805_6.3V6M
C169 2
1 1U_0402_6.3V4Z
C172 2
1 1U_0402_6.3V4Z
C175 2
1 1U_0402_6.3V4Z
C177 2
1 1U_0402_6.3V4Z
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
A
PM_EXTTS# 5,12
PM_SMBDATA 12,13,17,27
PM_SMBCLK 12,13,17,27
+0.75VS
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FOX_AS0A626-U2SN-7F_204P
@
4
3
2
Title
DDRIII-SODIMM0
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
11
of
45
B
+1.5V
C
+1.5V
2
DDR_B_DM0
1
DDR_B_D2
DDR_B_D3
2
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
close to JDDRH.1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
7
DDRB_CKE0
2
7
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
7
7
DDRB_CLK0
DDRB_CLK0#
DDR_B_MA10
7
DDR_B_BS0
7
7
DDR_B_W E#
DDR_B_CAS#
DDR_B_MA13
7
DDRB_SCS1#
DDR_B_D32
DDR_B_D33
3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R98 1
2
10K_0402_5%
4
+3VS
2.2U_0603_6.3V4Z
1
1
1 R99
2
10K_0402_5%
C207
C208
2
2
0.1U_0402_16V4Z
+0.75VS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
207
GND1
GND2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_B_D4
DDR_B_D5
7 DDR_B_DQS[0..7]
DDR_B_D6
DDR_B_D7
7 DDR_B_D[0..63]
DDR_B_D12
DDR_B_D13
7 DDR_B_DM[0..7]
1
7 DDR_B_MA[0..15]
DDR_B_DM1
SM_DRAMRST# 5,11
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1 7
DDR_B_MA15
DDR_B_MA14
2
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1 7
DDRB_CLK1# 7
DDR_B_BS1 7
DDR_B_RAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
+V_DDR3_DIMM_REF
R97
1
+DDR_VREF_CA_DIMMB
1
2
2 0_0402_5%
Layout Note:
Place near JDDRH
1
DDR_B_DQS#5
DDR_B_DQS5
Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB
Layout Note:
Place near JDDRH.203 and 204
3
+1.5V
+1.5V
@
C189 1
2
DDR_B_D44
DDR_B_D45
close to JDDRH.126
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
+0.75VS
2 330U_B2_2.5VM_R15M
C192 1
2 10U_0805_6.3V6M
C194 1
2 10U_0805_6.3V6M
C197 1
2 10U_0805_6.3V6M
C200 1
2 10U_0805_6.3V6M
C202 1
2 10U_0805_6.3V6M
C204 1
2 10U_0805_6.3V6M
C190 1
2 0.1U_0402_16V4Z
C193 1
2 0.1U_0402_16V4Z
C196 1
2 0.1U_0402_16V4Z
C199 1
2 0.1U_0402_16V4Z
C191 1
2 10U_0805_6.3V6M
C195 2
1 1U_0402_6.3V4Z
C198 2
1 1U_0402_6.3V4Z
C201 2
1 1U_0402_6.3V4Z
C203 2
1 1U_0402_6.3V4Z
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
4
PM_EXTTS# 5,11
PM_SMBDATA 11,13,17,27
PM_SMBCLK 11,13,17,27
+0.75VS
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FOX_AS0A626-UASN-7F_204P
@
A
7 DDR_B_DQS#[0..7]
DDR_B_DQS#0
DDR_B_DQS0
C188
0.1U_0402_16V4Z
1
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C187
2.2U_0603_6.3V4Z
1
C184
0.1U_0402_16V4Z
C183
2.2U_0603_6.3V4Z
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
E
Standard Type
DDR3 SO-DIMM B
JDDRH
+VREF_DQB
D
+
A
B
C
D
Title
DDRIII-SODIMM1
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
E
12
of
45
A
B
Clock Generator
C
D
E
F
G
H
+3VS_CK505
C211
C212
2
C251
47P_0402_50V8J
C219
C220
2
C221
For SED
R110
10K_0402_5%
+1.05VS_CK505
1
1
C222
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C252
47P_0402_50V8J
CK_PW RGD
D
1
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
FBMH1608HM601-T_0603
10U_0805_10V4Z
0.1U_0402_16V4Z
1
2
R101
1
1
1
+1.05VS
2
C210
+3VS_CK505
1
C209
R401
0_0603_5%
0.1U_0402_16V4Z
1
1
1
0.1U_0402_16V4Z
1
1
2
2
@
1
For SED
FBMH1608HM601-T_0603
1
2
R100
+3VS
1
For SED
2
For SED
0.1U_0402_16V4Z
1
1
1
C213
For SED
C214
2
1U_0402_6.3V4Z
2N7002_SOT23-3 S
+1.5VS_CK505
3
+1.5VS
FBMH1608HM601-T_0603
1
2
R126
C215
+3VS_CK505
Silego Have Internal Pull-Up
+1.05VS_CK505
+3VS_CK505
H_STP_CPU#
+1.5VS_CK505
26
10K_0402_5% 2
17
17
2
CLK_DOT
CLK_DOT#
1
CLK_48M_CR
CLK_48M_CR_R
2
R400 33_0402_5%
10K_0402_5% 2
1 R105
U5
+3VS_CK505
17
17
1
CLK_ENABLE# 42
2
2
0.1U_0402_16V4Z
Add C213 for NALA eSATA transmit issue
+1.05VS_CK505
2
G
Q37
CLK_SATA
CLK_SATA#
17 PCH_CLK_DMI
17 PCH_CLK_DMI#
H_STP_CPU#
1
2
3
4
5
6
7
8
VDD_USB_48
VSS_48M
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
USB_48
SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
VSS_27M
SATA
SATA#
VSS_SRC
SRC_1
SRC_1#
VDD_SRC_IO
CPU_STOP#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
24
23
22
21
20
19
18
17
33
PM_SMBCLK 11,12,17,27
PM_SMBDATA 11,12,17,27
CLK_14M_PCH 17
CPU_SEL 1
2
33_0402_5% R102
CLK_XTAL_IN
CLK_XTAL_OUT
CPU_SEL
@
1 R119
10K_0402_5% 2
+1.05VS
1 R106
IDT Have Internal Pull-Down
CK_PW RGD
CLK_BCLK 17
CLK_BCLK# 17
2
Remove C484 (for RF)
CLK_XTAL_OUT
+1.5VS_CK505
CPU_SEL
Y1
CLK_XTAL_IN
1
2
2
2
14.318MHZ_16PF_7A14300083
C223
C224
22P_0402_50V8J
22P_0402_50V8J
1
1
TGND
RTM890N-631-GRT QFN 32P
CPU_0/0#
CPU_1/1#
0 (Default)
133MHz
133MHz
1
100MHz
100MHz
LVDS / Int.Camera / Int.MIC Conn
0618 --> change camera power rail to +3VS
R107
150_0603_5%
R120
100K_0402_5%
+LCD_VDD
3
2
5
2
4
UMA_ENVDD
Q17
AO3413_SOT23
1
1
R109
1
3
1
2
2
47K_0402_5% 1
C229
0.01U_0402_25V7K
G
2
Q1B
2N7002DW -T/R7_SOT363-6
W=60mils
R112
100K_0402_5%
Camera
USB20_P11_R
USB20_N11_R
19
19
19
19
19
19
19
19
LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT1LCD_TXOUT2+
LCD_TXOUT2LCD_TXCLK+
LCD_TXCLK-
1
2
C233
0.1U_0402_16V4Z
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
32
GND1
GND2
3
@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
PACDN042Y3R_SOT23-3
LCD_EDID_CLK 19
LCD_EDID_DATA 19
INT_MIC_CLK
INT_MIC_DATA
3
INT_MIC_CLK 29
INT_MIC_DATA 29
PCH_PW M 19
BKOFF#_R
BKOFF#_R
+3VS
2
1
R137 33_0402_5%
1
+LCDVDD_R
+LCD_INV
2
BKOFF# 31
R113
10K_0402_5%
C232
0.1U_0402_16V4Z
B+
Rated Current MAX:600mA
ACES_87242-3001-09
1
UMA PD 100K ohm
DIS PD 10K ohm
D84 @
0.1U_0402_16V4Z
1
2
C231 CAM@
2
D
Q1A
2N7002DW -T/R7_SOT363-6
19
W=60mils
2
C228
0.1U_0402_16V7K
W=20mils
+3VS_LVDS_CAM
JLVDS
S
6 2
3
+3VS
0_0603_5%
R398 1
2
CAM@
1
+3VS
1
1
+3VS
2
+LCD_VDD
1.5A, 60mils
L2 2
1
FBMA-L11-201209-221LMA30T_0805
C234
68P_0402_50V8J
Reserve for EMI request
1
1
2
2
+LCDVDD_R
2 L1
1
0_0805_5%
1
C235
0.1U_0402_25V6
2
+LCD_VDD
1
C226
0.1U_0402_16V4Z
2
C227
4.7U_0805_10V4Z
R93 CAM@
1
2
0_0402_5%
4
4
L55 @
20
USB20_N11
1
20
USB20_P11
4
1
2
2
USB20_N11_R
4
3
3
USB20_P11_R
Issued Date
R92 CAM@
1
2
0_0402_5%
A
B
Compal Electronics, Inc.
Compal Secret Data
Security Classification
W CM-2012-900T_0805
2010/06/21
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
E
F
Title
Clock Generator (CK505)/ LVDS CONN
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
G
Sheet
13
of
H
45
A
B
C
D
E
D5
1
D4
1
D3
1
CRT CONNECTOR
+3VS
1
C239
2
3
2
L5
1
2
NBQ100505T-800Y_0402
CRT_B_L
1
C240
2
3
CRT_G_L
2
1
C241
2
1
C242
2
1
C243
2
2.2P_0402_50V8C
1
C238
L4
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
R140
1
CRT_R_L
2.2P_0402_50V8C
R139
2
2
R138
DAN217_SC59
@
L3
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
UMA_CRT_B
2.2P_0402_50V8C
19
2.2P_0402_50V8C
UMA_CRT_G
2
1
150_0402_1%
19
2
1
150_0402_1%
UMA_CRT_R
2
1
150_0402_1%
19
DAN217_SC59
@
3
DAN217_SC59
@
1
+5VS
+CRT_VCC_R
+CRT_VCC
F1
30mil
1
1
2
RB491D_SOT23-3
1
1.1A_6V_MINISMDC110F-2
C237
If=1A
@ 0.1U_0402_16V4Z
2
D6
2
3
2
2
+CRT_VCC
D_CRT_HSYNC
1
L6
2
10_0402_5%
HSYNC
D_CRT_VSYNC
1
L7
2
10_0402_5%
VSYNC
3
CRT_DDC_DAT
CRT_G_L
+CRT_VCC
1
2
P
OE#
5
1
C245
@
4
Y
C246
@
2
HSYNC
CRT_B_L
+CRT_VCC
VSYNC
CRT_DDC_CLK
G
A
2
1
10P_0402_50V8J
Y
U6
SN74AHCT1G125GW _SOT353-5
19 UMA_CRT_VSYNC
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
CRT_R_L
4
G
A
JCRT
1
10K_0402_5%
10P_0402_50V8J
2
19 UMA_CRT_HSYNC
2
R141
5
1
2
0.1U_0402_16V4Z
P
OE#
1
C244
G
G
16
17
ALLTO_C10532-11505-L_15P-T
@
3
U7
SN74AHCT1G125GW _SOT353-5
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
3
3
+3VS
1
Q2B
4
19 UMA_CRT_CLK
1
C247
33P_0402_50V8K
2
@
1
5
19 UMA_CRT_DATA
1
將R146 and R147阻阻阻阻2.2k-ohm
R147
2.2K_0402_5%
2
R146
2.2K_0402_5%
2
Q2A
2
1
+CRT_VCC
6
CRT_DDC_DAT
2N7002DW -T/R7_SOT363-6
CRT_DDC_CLK
3
2N7002DW -T/R7_SOT363-6
C249
C248
470P_0402_50V8J
33P_0402_50V8K
@
2 @
1
1
2
C250
470P_0402_50V8J
2 @
4
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
CRT\TV\LVDS
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
E
14
of
45
5
4
3
2
1
0624 --> Remove BIOS ROM Debug Circuit
D
D
C
C
B
B
A
A
2010/06/21
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
BIOS ROM Debug
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
15
of
45
4
OSC
4
NC
OSC
1
32.768KHZ_12.5PF_Q13MC14610002
2
2
1U_0402_6.3V4Z
2
C290
1
15P_0402_50V8J
D
+RTCVCC
Integrated SUS 1.05V VRM Enable
1
R285
1
R275
High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
+RTCVCC
B13
D13
RTCX1
RTCX2
PCH_RTCRST#
C14
RTCRST#
SRTCRST#
SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
HDA_SYNC
AZ_SYNC
D29
HDA_SYNC
This signal has a weak internal pull down.
H=>On Die PLL is supplied by 1.5V
Die PLL is supplied by 1.8V
PCH_SPKR
HDA_SDO
P1
29 AZ_SDIN0_HD
remove SDN1 for MDC
This signal has a weak internal pull down.
This signal can't PU
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
@ R118 1K_0402_5%
1
2
*
AZ_SDOUT
HDA_SDIN3
B29
HDA_SDO
31 PW RME_CTRL#
remove CR_CPPE# for JM385
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
R288 1
29 AZ_BITCLK_HD
R290 1
29 AZ_SYNC_HD
ITPM Enabled
SPI_MOSI
PCH_JTAG_TCK
M3
JTAG_TCK
PCH_JTAG_TMS
K3
JTAG_TMS
PCH_JTAG_TDI
K1
JTAG_TDI
PCH_JTAG_TDO
J2
JTAG_TDO
PCH_JTAG_RST#
J4
TRST#
AZ_SYNC
2 33_0402_5%
R294 1
29 AZ_SDOUT_HD
AZ_BITCLK
2 33_0402_5%
R292 1
29 AZ_RST_HD#
B
2 33_0402_5%
AZ_RST#
2 33_0402_5%
AZ_SDOUT
FWH4 / LFRAME#
C34
LPC_FRAME# 31,32
LDRQ0#
LDRQ1# / GPIO23
A34
F34
SERIRQ
AB9
Internal: Pull down 20k
High = Enabled
Low = Disabled (Default)
2
R273
@
AH6
AH5
AH9
AH8
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF11
AF9
AF7
AF6
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AH3
AH1
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD9
AD8
AD6
AD5
31,32
+3VS
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AD3
AD1
AB3
AB1
SATAICOMPO
AF16
SATAICOMPI
AF15
SATA_PRX_C_DTX_N4 25
SATA_PRX_C_DTX_P4 25
SATA_PTX_DRX_N4 25
SATA_PTX_DRX_P4 25
SATA ODD
+3VS
SATAICOMP
1
R295
SPI_CS1#
SATALED#
T3
SATA_LED#
AY1
SPI_MOSI
SATA0GP / GPIO21
Y9
PCH_GPIO21
SATA1GP / GPIO19
V1
PCH_GPIO19
SPI_MISO
1ST HDD
remove eSATA SATA
SPI_CS0#
2
37.4_0402_1%
+1.05VS
PCH_GPIO21
R302 2
1 10K_0402_5%
SATA_LED#
R301 2
1 10K_0402_5%
PCH_GPIO19
R306 1
2 10K_0402_5%
B
HM55R1@
4MB
For EMI
Place near U13
1
PCH_JTAG_RST#
R385
@ 10_0402_5%
2
@
R364
10K_0402_5%
PCH_SPI_CLK
@
C16
10P_0402_50V8J
C293
0.1U_0402_16V4Z
2
1
U13
8
VCC
3
W
7
HOLD
PCH_SPI_CS0#
1
S
PCH_SPI_CLK
6
C
PCH_SPI_MOSI
5
D
VSS
4
Q
2
PCH_SPI_MISO
MX25L3205DM2I-12G SO8
2
1
R156
D
+3VS
@
R643
20K_0402_5%
1
1
@
R537
100_0402_5%
2
C
1
2
2
PCH_JTAG_TDI
CHN202UPT SC-70
Desktop Only
AY3
AV1
SERIRQ
2
10K_0402_5%
SATA_PRX_C_DTX_N1 25
SATA_PRX_C_DTX_P1 25
SATA_PTX_DRX_N1 25
SATA_PTX_DRX_P1 25
SPI_CLK
2
@
R535
100_0402_5%
1
PCH_JTAG_TDO
@
R536
200_0402_5%
2
@
R355
100_0402_5%
@
R363
200_0402_5%
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
+3VALW
1
1
2
1
PCH_JTAG_TMS
+3VALW
2
1
2
@
R386
200_0402_5%
2
1
+3VALW
AK7
AK6
AK11
AK9
AV3
IBEXPEAK-M QV20 A0_FCBGA1071
+3VALW
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
BA2
1PCH_SPI_MOSI
1K_0402_5%
PCH_SPI_MISO
C291
0.1U_0402_16V4Z
@ JRTC
LOTES_AAA-BAT-054-K01
SERIRQ
PCH_SPI_CS0#
+3VS
31,32
31,32
31,32
31,32
remove FELICA_PWR#
PCH_SPI_CLK
SPI
HDA_DOCK_EN#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SPKR
C30
Flash Descriptor Security Overide
Low = Enabled
High = Disabled
D33
B33
C32
A32
-
AZ_BITCLK
C
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
1
R286
AZ_RST#
3
1
PCH_RTCX1
PCH_RTCX2
D17
19,29 PCH_SPKR
+3VL
1
PCH_SRTCRST#
*L=>On
+RTCBATT
D10
2
U11A
2
1
2PCH_SRTCRST# 1
R284 20K_0402_1%
1
C289
NC
2
1
J2
3
LPC
iME Setting.
Y3
2
1U_0402_6.3V4Z
SATA
1
C288
1
RTC schematic for non-chargeable
RTC
2
IHDA
1
2
JTAG
1
2PCH_RTCRST#
R282 20K_0402_1%
R283
10M_0402_5%
2
1
CMOS Setting, near DDR Door
JCMOS
+RTCVCC
3
C287
15P_0402_50V8J
2
1
+
5
PCH_JTAG_TCK
2
51_0402_5%
06/01 change R125 from 4.7K to 51 ohm
A
PCH Pin
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TCK
PCH_JTAG_RST#
PCH JTAG Enable
ES1
ES2
No Install
200ohm
No Install
100ohm
200ohm
200ohm
100ohm
100ohm
200ohm
200ohm
100ohm
100ohm
51ohm
51ohm
20Kohm
20Kohm
10Kohm
10Kohm
RefDes
R358
R535
R355
R354
R536
R537
R156
R643
R353
5
A
PCH JTAG Disable (Default)
ES1
ES2
No Install
No Install
No Install
No Install
No Install
No Install
No Install
No Install
20Kohm
No Install
10Kohm
No Install
51ohm
51ohm
No Install
No Install
No Install
No Install
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Title
PCH-SPI/SATA/LPC/RTC/HDA
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
16
of
45
4
3
2
1
2 R229
2 R230
+3VALW
+3VS
1 2.2K_0402_5%
1 2.2K_0402_5%
Q3B
PCH_SMBDATA
R231
R232
5
5
PM_SMBDATA 11,12,13,27
2N7002DW -T/R7_SOT363-6
Q3A
PCH_SMBCLK
4
2
3
4.7K_0402_5%
4.7K_0402_5%
6
1
PM_SMBCLK 11,12,13,27
2N7002DW -T/R7_SOT363-6
U11B
AU30
AT30
AU32
AV32
PERN3
PERP3
PETN3
PETP3
remove NewCard PCIE
remove JET PCIE
remove CardReader PCIE
C
NC
LAN
28
28
CLK_LAN#
CLK_LAN
CLKREQ_LAN#
28 CLKREQ_LAN#
WLAN
27
27
CLKREQ_W LAN#
27 CLKREQ_W LAN#
remove NEWCARD CLK
B
+3VS
1
10K_0402_5%
1
10K_0402_5%
2
R244
PCH_GPIO20
2
R248
CLKREQ_W LAN#
BA32
BB32
BD32
BE32
PERN4
PERP4
PETN4
PETP4
BF33
BH33
BG32
BJ32
PERN5
PERP5
PETN5
PETP5
BA34
AW34
BC34
BD34
PERN6
PERP6
PETN6
PETP6
AT34
AU34
AU36
AV36
PERN7
PERP7
PETN7
PETP7
BG34
BJ34
BG36
BJ36
PERN8
PERP8
PETN8
PETP8
AK48
AK47
CLKOUT_PCIE0N
CLKOUT_PCIE0P
P9
AM43
AM45
CLK_W LAN#
CLK_W LAN
form CLKREQ_NEW# to PCH_GPIO20
U4
AM47
AM48
PCH_GPIO20
N4
remove JET CLK
AH42
AH41
PCH_GPIO25
A8
AM51
AM53
PCH_GPIO26
SMBDATA
M9
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCH_SMBCLK
C8
PCH_SMBDATA
SML0CLK
C6
PCH_SMLCLK0
SML0DATA
G8
PCH_SMLDATA0
SML1ALERT# / GPIO74
M14
PCH_GPIO74
SML1CLK / GPIO58
E10
PCH_SMLCLK1
SML1DATA / GPIO75
G12
PCH_SMLDATA1
CL_CLK1
T13
CL_DATA1
T11
CL_RST1#
T9
H1
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
AT1
AT3
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
AJ50
AJ52
CLKREQ_LAN#
PCH_GPIO44
1
10K_0402_5%
2
R245
PCH_GPIO25
1
10K_0402_5%
2
R249
PCH_GPIO26
1
10K_0402_5%
2
R250
PCH_GPIO44
1
10K_0402_5%
2
R251
PCH_GPIO56
AK53
AK51
form CLKREQ_CR# to PCH_GPIO26
PCH_GPIO56
A
H6
form CLKREQ_JET# to PCH_GPIO25
P13
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
Clock Flex
2
R246
CLKREQ_PEG#
1
R260
2
10K_0402_5%
1
EC_SMB_CK2 31
PCH_SMLCLK0
PCH_SMLDATA0
PCH_GPIO60
PCH_GPIO74
EC_LID_OUT#
+3VALW
2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
2
2
2
1
1
1
1
1
R237
R238
R239
R240
R241
CLK_PEG# 5
CLK_PEG 5
AP3
AP1
CLK_BCLK# 13
CLK_BCLK 13
CLKIN_DOT_96N
CLKIN_DOT_96P
F18
E18
CLK_DOT# 13
CLK_DOT 13
AH13
AH12
CLK_SATA# 13
CLK_SATA 13
P41
CLK_14M_PCH 13
CLKIN_PCILOOPBACK
EC_SMB_DA2 31
+3VALW
CLKIN_BCLK_N
CLKIN_BCLK_P
REFCLK14IN
6
4
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
PCH_CLK_DMI# 13
PCH_CLK_DMI 13
XTAL25_IN
XTAL25_OUT
AH51
AH53
XCLK_RCOMP
AF38
CLKOUTFLEX0 / GPIO64
T45
CLKOUTFLEX1 / GPIO65
P43
CLKOUTFLEX2 / GPIO66
T42
CLKOUTFLEX3 / GPIO67
N50
FROM CLK GEN FOR: 133/100/96/14.318 MHZ
B
R247
2
2
PCH_X2
1
27P_0402_50V8J
2
2
C277
PCH_X1
PCH_X2
1
25MHZ_20PF_7A25000012 1
CLK_PCILOOP 20
XCLK_RCOMP 1
2
R252 90.9_0402_1%
1M_0402_5%
1
Y2
PCH_X1
J42
+3VALW
1
10K_0402_5%
3
PCH_SMLCLK1
AW24
BA24
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
Q4B
PCH_SMLDATA1
AD43
AD45
AN4
AN2
CLKIN_DMI_N
CLKIN_DMI_P
+3VS
1 2.2K_0402_5%
1 2.2K_0402_5%
C
CLKOUT_DMI_N
CLKOUT_DMI_P
PCIECLKRQ3# / GPIO25
2 R233
2 R234
+3VALW
Q4A
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PCIECLKRQ2# / GPIO20
EC_LID_OUT# 31
PCH_GPIO60
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
H14
J14
SML0ALERT# / GPIO60
PCIECLKRQ0# / GPIO73
EC_LID_OUT#
5
PERN2
PERP2
PETN2
PETP2
SMBCLK
B9
2
AW30
BA30
PCIE_PTX_W LANRX_N2 BC30
PCIE_PTX_W LANRX_P2 BD30
SMBALERT# / GPIO11
SMBus
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PERN1
PERP1
PETN1
PETP1
Link
C274 2
C275 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
Controller
For WLAN
PCIE_PRX_W LANTX_N2
PCIE_PRX_W LANTX_P2
PCIE_PTX_C_W LANRX_N2
PCIE_PTX_C_W LANRX_P2
C371 2
C340 2
D
PEG
27
27
27
27
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
BG30
BJ30
BF29
BH29
PCI-E*
28
28
28
28
For LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
From CLK BUFFER
D
C278
27P_0402_50V8J
+1.05VS
C277
@
0_0402_5%
Note: Stuff 0 ohm if
25MHz crystal un-stuff
for EMI request
@
IBEXPEAK-M QV20 A0_FCBGA1071
CLK_PCILOOP
@
1
R125
2
10_0402_5%
HM55R1@
CLK_14M_PCH
@
1
2
R70
100_0402_5%
1
2
C265 22P_0402_50V8J
@
2
1
A
C206 100P_0402_50V8J
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
CLK/PCIE/SMBUS
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
17
of
45
5
4
3
2
1
D
D
PCH_SUSPW RDN
2
10K_0402_5%
PCH_LOW _BAT#
2
10K_0402_5%
IBEX_RI#
2
10K_0402_5%
BC24
BJ22
AW20
BJ20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
6
6
6
6
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BD24
BG22
BA20
BG20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
6
6
6
6
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
BE22
BF21
BD20
BE18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
6
6
6
6
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
BD22
BH21
BC20
BD18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
1
R311
+1.05VS
PM_PW ROK
1
10K_0402_5%
PW ROK
1
10K_0402_5%
LAN_RST#
1
10K_0402_5%
2
R329
2
R322
2
R323
C
BH25
BF25
Close to PCH
@
2
0_0402_5%
DMI_ZCOMP
5 XDP_DBRESET#
5
31,42
XDP_DBRESET#
T6
VGATE
VGATE
M6
PW ROK
4
O
B17
SN74AHC1G08DCKR_SC70-5
1
R321
2
0_0402_5%
LAN_RST#
K5
A10
D9
5 DRAMPW ROK
PCH_RSMRST#
31 PCH_SUSPW RDN
C16
PCH_SUSPW RDN
31 PBTN_OUT#
31,37
ACIN
1
R324
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
6
6
6
6
6
6
6
6
FDI_INT
BJ14
FDI_INT
FDI_FSYNC0
BF13
FDI_FSYNC0
FDI_FSYNC1
BH13
FDI_FSYNC1
6
FDI_LSYNC0
BJ12
FDI_LSYNC0
6
FDI_LSYNC1
BG14
FDI_LSYNC1
6
PCH_ACIN
2
330K_0402_5%
D26
1
2
1
CH751H-40PT_SOD323-2
R330 @
2
ACIN_D 31
PCH_LOW _BAT#
PCH_W AKE#
CLKRUN# / GPIO32
Y1
PM_CLKRUN#
PWROK
MEPWROK
SUS_STAT# / GPIO61
P8
SUS_STAT#
SUSCLK / GPIO62
F3
EC_CLK
LAN_RST#
SLP_S5# / GPIO63
E4
DRAMPWROK
PM_SLP_S5# 31
SLP_S4#
H7
RSMRST#
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
+3VALW
2
1K_0402_5%
PM_SLP_S4# 31
SLP_S3#
P12
PM_SLP_S3# 31
SLP_M#
K8
TP23
N2
PCH_W AKE#
PCH_W AKE# 28
2
R319
1
8.2K_0402_5%
2 R325
1
Q26 1
@
E
MMBT3906_SOT23-3
2
B
RSMRST# circuit
BJ10
PMSYNCH
RI#
1
10K_0402_5%
+3VALW
+3VS
PADT38
PADT38
EC_CLK 31
For EC Crystal cost down
PMSYNCH
5
F6
SLP_LAN# / GPIO29
2
1
HM55R1@
PCH_RSMRST#
0716 --> Unmount : R327, Q26,
D15A, D15B, R328, R690
Mount : R325, D29, D28
CH751H-40PT_SOD323-2
D28
36,38
POK
1
2
CH751H-40PT_SOD323-2
5
4
2
1
2
A
for abnormal shutdowm from s3 resume
1
2
@ R328
2.2K_0402_5%
Compal Electronics, Inc.
Compal Secret Data
Security Classification
3
D15B @
BAV99DW -7_SOT363
6
1
R327
@ 4.7K_0402_5%
@ D15A
BAV99DW -7_SOT363
PW ROK
PCH_RSMRST#
2
1
R326
10K_0402_5%
C
3
31 EC_RSMRST#
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
2
R313
D29
0_0402_5%
+3VALW
C
B
M1
IBEXPEAK-M QV20 A0_FCBGA1071
A
6
0_0402_5%
IBEX_RI#
1
@ R690
6
J12
SYS_PWROK
B
+3VALW
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
WAKE#
IN2
3
2
6
6
6
6
6
6
6
6
SYS_RESET#
P
VGATE
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
1
R256
+3VS
0.1U_0402_16V4Z
1
2
C272
U12
1 IN1
PM_PW ROK
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
DMI_IRCOMP
G
31
DMI_COMP
2
49.9_0402_1%
System Power Management
1
R316
1
R318
1
R320
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI
+3VALW
6
6
6
6
DMI
U11C
4
3
2
Title
PCH-DMI/FDI/PWM
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
18
of
45
5
4
3
2
1
U11D
PCH_PW M
D
2
R59
2
R60
LCD_EDID_DATA
1
2.2K_0402_5%
LCTL_CLK
2
AB46
2 10K_0402_5% LCTL_DATA
V48
10K_0402_5%
LVDS_IBG
2
AP39
2.37K_0402_1%
AP41
T15 PAD
AT43
AT42
1
R55
2
R63
UMA_CRT_CLK
1
2.2K_0402_5%
2
R61
UMA_CRT_DATA
1
2.2K_0402_5%
1
R56
1
R57
1
R58
2
150_0402_1%
2
150_0402_1%
2
150_0402_1%
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
13 LCD_TXOUT013 LCD_TXOUT113 LCD_TXOUT2-
BB47
BA52
AY48
AV47
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
13 LCD_TXOUT0+
13 LCD_TXOUT1+
13 LCD_TXOUT2+
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AP48
AP47
LVDSB_CLK#
LVDSB_CLK
AY53
AT49
AU52
AT53
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
AA52
AB53
AD53
CRT_BLUE
CRT_GREEN
CRT_RED
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
V51
V53
CRT_DDC_CLK
CRT_DDC_DATA
14 UMA_CRT_HSYNC
14 UMA_CRT_VSYNC
Y53
Y51
CRT_HSYNC
CRT_VSYNC
1CRT_IREF
1K_0402_1%
SDVO_STALLN
SDVO_STALLP
BJ48
BG48
SDVO_INTN
SDVO_INTP
BF45
BH45
AD48
AB51
DAC_IREF
CRT_IRTN
T51
T53
D
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
BG44
BJ44
AU38
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
DDPC_CTRLCLK
DDPC_CTRLDATA
Y49
AB49
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
BE44
BD44
AV40
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
DDPD_CTRLCLK
DDPD_CTRLDATA
14 UMA_CRT_CLK
14 UMA_CRT_DATA
2 R266
BJ46
BG46
SDVO_CTRLCLK
SDVO_CTRLDATA
AV53
AV51
14
14
14
SDVO_TVCLKINN
SDVO_TVCLKINP
L_CTRL_CLK
L_CTRL_DATA
13 LCD_TXCLK13 LCD_TXCLK+
+3VS
C
L_DDC_CLK
L_DDC_DATA
1
1 R1433
R54
+3VS
LCD_EDID_CLK
1
2.2K_0402_5%
L_BKLTCTL
AB48
Y45
13 LCD_EDID_CLK
13 LCD_EDID_DATA
+3VS
L_BKLTEN
L_VDD_EN
Digital Display Interface
13
T48
T47
Y48
LVDS
EC_ENBKL
31 EC_ENBKL
13 UMA_ENVDD
EC_ENBKL
2
100K_0402_5%
BC46
BD46
AT38
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
IBEXPEAK-M QV20 A0_FCBGA1071
R68
100K_0402_5%
1
2
For INTEL issue (pending interrupts from the PCH for unused HDMI ports)
R343 100K_0402_5%
1
2
C
U50
U52
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT
1
R124
R77
1
100K_0402_5%
2
HM55R1@
PCH Strap Pin
B
B
Internal: Pull down 20k
During Reset: HZ
Initial: Low
+3VS
@
PCH_SPKR
1
2
R269
1K_0402_5%
1K_0402_5% 2
@
1 R270
PCI_GNT#0
1K_0402_5% 2
@
1 R271
PCI_GNT#1
@
1
1K_0402_5%
PCI_GNT#3
PCH_SPKR
PCI_GNT#0 20
PCI_GNT#1 20
+1.8VS_PCH_NAND
Low= Disable
High= Enable
0
0
1
1
0
1
0
1
Boot BIOS Loaction
@
1
1K_0402_5%
NV_ALE
NV_ALE 20
2
R268
@
NV_CLE
1
1K_0402_5%
NV_CLE 20
LPC
Reserved (NAND)
PCI
SPI (Default)
Internal: Pull down 20k
During Reset: Low
Initial: Low
High = Enabled
Low = Disabled (Default)
DMI Termination Voltage
NV_CLE
Low= Set to Vss (Default)
High= Set to Vcc
PCI_GNT#3 20
Internal: Pull up 20k
During Reset: High
Initial: High
A16 Swap Override Strap
PCI_GNT#3
A
Low= A16 swap override Enable
High= A16 swap override Disable
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Danbury Technology Enabled
NV_ALE
2
R267
Boot BIOS Strap
PCI_GNT#1 PCI_GNT#0
Internal: Pull up 20k
During Reset: High
Initial: High
2
R272
NO REBOOT Strap
PCH_SPKR 16,29
Internal: Pull up 20k
During Reset: High
Initial: High
Internal: Pull down 20k
During Reset: Low
Initial: Low
4
3
2
Title
PCH-CRT/LVDS/HDMI
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
19
of
45
2
1
1
R253
2
0_0402_5%
U11E
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
F51
A46
B45
M53
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
F48
K45
F36
H53
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
B41
K53
A36
A48
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
RP2
1
2
3
4
C
8
7
6
5
PCI_PIRQH#
PCI_TRDY#
PCI_FRAME#
PCI_PIRQA#
8.2K_0804_8P4R_5%
RP3
1
2
3
4
8
7
6
5
PCI_STOP#
PCI_PIRQE#
PCI_PIRQC#
PCI_PIRQG#
8.2K_0804_8P4R_5%
GNT2#: Not pull low, internal pull up 20K
19
19
PCI_GNT#0
PCI_GNT#1
19
PCI_GNT#3
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
+3VS
RP4
1
2
3
4
B
8
7
6
5
T37 PAD
PCI_REQ#3
PCI_PIRQF#
PCI_PIRQB#
PCI_REQ#0
8.2K_0804_8P4R_5%
+3VS
TP_PCI_RST#
8
7
6
5
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PLOCK#
SERR#
PERR#
PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#
A42
H44
F46
C46
IRDY#
PAR
DEVSEL#
FRAME#
PCI_PLOCK#
D49
PLOCK#
PCI_STOP#
PCI_TRDY#
8.2K_0804_8P4R_5%
27,28,31,32 PLT_RST#
32 CLK_PCI_DDR
31 CLK_PCI_EC
17 CLK_PCILOOP
PCIRST#
E44
E50
RP5
1
2
3
4
K6
PCI_SERR#
PCI_PERR#
2
1 CLK_SIO
22_0402_5%
R280
2
1 CLK_EC
22_0402_5%
R281
2
1 CLK_PCH
22_0402_5% R279
D41
C48
STOP#
TRDY#
M7
PME#
D5
PLTRST#
N52
P53
P46
P51
P48
NV_ALE
NV_CLE
BD3
AY6
NV_RCOMP
AU2
NV_RB#
AV7
NV_WR#0_RE#
NV_WR#1_RE#
AY8
AY5
NV_WE#_CK0
NV_WE#_CK1
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
IN1
1
D
IN2
2
O
PLT_RST#
R51
100K_0402_5%
SN74AHC1G08DCKR_SC70-5
R129
100K_0402_5%
@
NV_ALE 19
NV_CLE 19
NV_RCOMP
@
1
2
R276
32.4_0402_1%
C
AV11
BF5
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
USBRBIAS#
B25
USBRBIAS
D25
USBBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
N16
J16
F16
L16
E14
G16
F12
T15
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
EXP_CPPE#
IBEXPEAK-M QV20 A0_FCBGA1071
4
5 BUF_PLT_RST#
C477
0.1U_0402_16V4Z
1
2
@
P
G38
H51
B37
A44
8.2K_0804_8P4R_5%
U8
G
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
add PCI_REQ#2 for non-ODD_EN#
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
USB
PCI_REQ#1
PCI_REQ#2
PCI_PIRQD#
PCI_IRDY#
PCI
8
7
6
5
NV_DQS0
NV_DQS1
AV9
BG8
+3VS
3
C/BE0#
C/BE1#
C/BE2#
C/BE3#
RP1
1
2
3
4
AY9
BD1
AP15
BD8
1
J50
G42
H47
G34
+3VS
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
NVRAM
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
D
2
3
1
4
5
5
USB20_N0
USB20_P0
USB20_N1
USB20_P1
25
25
25
25
USB-LIGHT1
USB-LIGHT2
USB-Left1
remove eSATA
remove NewCard
remove BT
HM55 USB port6/7 NC
remove FingerPr
remove FELICA
USB20_N10
USB20_P10
USB20_N11
USB20_P11
26
26
13
13
B
Card reader(2 in 1)
Int. Camera
remove 3G/TV#1
USB20_N13 27
USB20_P13 27
WiMax(WLAN)
+3VALW
2
R278
1
22.6_0402_1%
Within 500 mils
RP6
USB_OC#6
USB_OC#4
USB_OC#0
USB_OC#5
(USB-Right)
USB_OC#0 25,31
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
RP8
USB_OC#2
USB_OC#1
USB_OC#3
EXP_CPPE#
HM55R1@
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
A
2
Title
PCH USB/PCI/NAND
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
20
of
45
5
4
3
2
1
pull down 100k to GND
U11F
PCH_GPIO6
D37
TACH2 / GPIO6
LAN_PHY_PWR_CTRL / GPIO12
A20GATE
PCH_GPIO15
T7
GPIO15
PCH_GPIO16
AA2
SATA4GP / GPIO16
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AM3
CLK_CPU_BCLK# 5
PCH_GPIO17
F38
TACH0 / GPIO17
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AM1
CLK_CPU_BCLK 5
TACH3 / GPIO7
F10
GPIO8
PCH_GPIO27
1
1K_0402_5%
PCH_GPIO28
PROJECT_ID
NBQAA 11.6/13.3"
C
NBQAA 14"
ID0
ID1
L
L
L
27
H
L
NALAA 17.3"
H
H
remove BT_RST#
5
+3VS
1
2 PCH_GPIO1
10K_0402_5% R214
1
2 PCH_GPIO6
10K_0402_5% R218
EC_SCI#
1
2
10K_0402_5% R224
1
2 PCH_GPIO16
10K_0402_5% R221
1
2 PCH_GPIO17
10K_0402_5% R220
BT_DET#
1
2
8.2K_0402_5% R215
1
2 PCH_GPIO38
10K_0402_5% R217
1
2 PCH_GPIO39
10K_0402_5% R254
1
2 PROJECT_ID0
10K_0402_5% R255
1
2 PROJECT_ID1
10K_0402_5% R216
1
2 PCH_GPIO48
10K_0402_5% R257
1
2 THM_ALT#
10K_0402_5% R259
B
1
2
10K_0402_5%
BT_PW R#
R261
BT_PW R#
31
RST_GATE
THM_ALT#
A
1
R416
1
R415
@
@
GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
V6
PROJECT_ID1
AB13
PECI
RCIN#
U2
T1
PROCPWRGD
BE10
THRMTRIP#
BD10
TP1
BA22
SATA3GP / GPIO37
TP2
AW22
SATA2GP / GPIO36
SLOAD / GPIO38
TP3
BB22
P3
SDATAOUT0 / GPIO39
TP4
AY45
LVDS_SEL
H3
PCIECLKRQ6# / GPIO45
TP5
AY46
RST_GATE
F1
PCIECLKRQ7# / GPIO46
TP6
AV43
PCH_GPIO48
AB6
SDATAOUT1 / GPIO48
TP7
AV45
THM_ALT#
AA4
SATA5GP / GPIO49
TP8
AF13
GPIO57
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
TP13
AK42
TP14
M32
TP15
N32
TP16
M30
TP17
N30
TP18
H12
TP19
AA23
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
NC_5
T39
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
change Netname from
RF_OFF# to PCH_GPIO17
change R254 to 10k and
Netname from CIR_EN# to PCH_GPIO39
change Netname from
ISDBT_DET to PCH_GPIO39
add R261 10k
for BT fun
PECI
KB_RST#
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V#
TP24
IBEXPEAK-M QV20 A0_FCBGA1071
HM55R1@
LVDS_SEL=H
for Single Channel LVDS
5
KB_RST# 31
H_PW RGOOD 5
THRMTRIP_PCH#
1
R212
2
56_0402_1%
H_THERMTRIP# 5
1
R210
2
+VTT
56_0402_1%
C
V3
F8
GATEA20 31
SATACLKREQ# / GPIO35
PCH_GPIO39
PCH_GPIO57
GATEA20
BG10
PCH_GPIO38
P6
C10
B
Not pull low
internal pull up
Internal: Pull up 20k
During Reset: High
Initial: High
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2 PROJECT_ID0
10K_0402_5%
2 PROJECT_ID1
10K_0402_5%
5
SCLOCK / GPIO22
H10
AB7
+3VALW
EC_SMI#
1
2
R225
10K_0402_5%
1
2 PCH_GPIO57
R226
10K_0402_5%
1
2 PCH_GPIO15
R227
1K_0402_5%
1
2 PCH_GPIO28
R242
10K_0402_5%
1
2 LVDS_SEL
R222
10K_0402_5%
1
2 RST_GATE
R223
10K_0402_5%
1
2 PCH_GPIO12
10K_0402_5% R219
Y7
PROJECT_ID0
H
*NWQAA 16"
D
K9
J32
EC_SMI#
BT_DET#
Name
AF48
AF47
PCH_GPIO12
EC_SCI#
EC_SMI#
@
AH45
AH46
CLKOUT_PCIE7N
CLKOUT_PCIE7P
EC_SCI#
2
R274
CLKOUT_PCIE6N
CLKOUT_PCIE6P
MISC
TACH1 / GPIO1
31
On-Die PLL VR
PCH_GPIO27
C38
31
Internal: Pull down 20k
During Reset: Low
Initial: Low
High = Enabled (Default)
Low = Disabled
BMBUSY# / GPIO0
PCH_GPIO1
CPU
GPIO15
a Strong pull up may be needed
for GPIO Functionality
Y3
RSVD
Internal: Pull up 20k
During Reset: High
Initial: High
D
PCH_HDMI_HPD
GPIO
Not pull down
NCTF
R189 100K_0402_5%
1
2
GPIO8
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Title
PCH CPU/GPIO
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
21
of
45
5
4
3
2
1
Add R52 for CRT wave issue at pre-MP
+1.05VS
2
1
C294
1U_0402_6.3V4Z
2
2
C310
B
VCCAPLLEXP
VCCIO[54]
VCCIO[55]
AN35
VCC3_3[1]
+PCH_VRM
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
+1.05VS
AM23
1
0.1U_0402_16V4Z
VCCIO[1]
LVDS
40mA
AF53
VSSA_DAC[2]
AF51
C296
0.01U_0402_25V7K
AH39
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
AP43
AP45
AT46
AT45
2
C298
10U_0805_10V4Z
L12
2
1
2.2_0603_1%
Change L12 to 2.2 ohm
for CRT issue at pre-MP
D
+3VS
+1.8VS
+3VS
HVCMOS
1
1
C297
0.1U_0402_16V4Z
R52
1
2
0_0603_5%
close to AE50
AH38
375mA
VCC3_3[2]
AB34
VCC3_3[3]
AB35
VCC3_3[4]
AD35
C300
0.01U_0402_25V7K
C299
0.01U_0402_25V7K
2
0.1U_0402_16V4Z
C303
1
close to AB34
C
+PCH_VRM
196mA
3062mA
DMI
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
AN30
AN31
+3VS
VSSA_DAC[1]
+3VS_VCCADAC
2
VCCALVDS
61mA
PCI E*
2
10U_0805_10V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
AE52
VSSA_LVDS
156mA
375mA
37mA
VCCVRM[2]
AT24
VCCDMI[1]
AT16
VCCDMI[2]
AU16
+VTT
+PCH_VRM
+PCH_VCCDMI
1
2
NAND / SPI
BJ24
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
VCCIO[24]
FDI
AK24
1
C304
1
C305
1
C306
1
C307
1
C308
VCCADAC[2]
> 1mA
59mA
+1.05VS
AE50
1432mA
+1.05VS
C
VCCADAC[1]
69mA
CRT
D
1
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCC CORE
C295
10U_0805_10V4Z
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
+3VS
POWER
U11G
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
1
R335
+1.8VS
2
0_0603_5%
C309
1U_0402_6.3V4Z
2
R336
1
0_0402_5%
close to AT16
+1.8VS_PCH_NAND
+1.8VS
1
R338
2
2
0_0603_5%
C311
0.1U_0402_16V4Z
1
close to Ak13
B
+3VS
85mA
IBEXPEAK-M QV20 A0_FCBGA1071
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
HM55R1@
AM8
AM9
AP11
AP9
2
C313
close to AM8
0.1U_0402_16V4Z
1
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PCH POWER-1
Size
B
Date:
Document Number
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
1
22
of
45
3
POWER
2
2
1
C323
22U_0805_6.3V6M
2
2
1
C327
+1.05VS
VCCME[2]
AD41
VCCME[3]
AF43
VCCME[4]
AF41
VCCME[5]
C324
1U_0402_6.3V4Z
+VCCRTCEXT
2
0.1U_0402_16V4Z
VCCME[6]
V39
VCCME[7]
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
VCCME[12]
V9
DCPRTC
R349 0_0603_5%
1
2
R347
0_0603_5%
@
C80
10U_0805_10V4K
+1.05VS_PCHDPLL_A
2
2
L18 1
2
10UH_LB2012T100MR_20%
1
2
1
VCCVRM[3]
1
C329
1U_0402_6.3V4Z
196mA
AU24
+PCH_VRM
1
C332
1U_0402_6.3V4Z
2
change cap to 10uf for cost
+1.05VS
1
C334
1U_0402_6.3V4Z
163mA
1849mA
AF42
1
Reseve R349 for L17 Filter Cap.
C
VCCME[1]
AD39
68mA
BB51
BB53
VCCADPLLA[1]
VCCADPLLA[2]
69mA
+1.05VS_PCHDPLL_B
BD51
BD53
VCCADPLLB[1]
VCCADPLLB[2]
1U_0402_6.3V4Z
1
1
AH23
AJ35
AH35
VCCIO[21]
VCCIO[22]
VCCIO[23]
AF34
VCCIO[2]
C335
2
C336
2
2
1U_0402_6.3V4Z
Short AF34, AH34 and AF32 power
for HDMI Deep Color
AH34
VCCIO[3]
AF32
VCCIO[4]
1
C338
+VCCSST
2
0.1U_0402_16V4Z
V12
DCPSST
1
C341
2 +V1.1A_INT_VCCSUS Y22
0.1U_0402_16V4Z
DCPSUS
VCCSUS3_3[28]
U23
VCCIO[56]
V23
+1.05VS
V5REF_SUS
F24
+PCH_VCC5REFSUS
> 1mA
> 1mA
375mA
V5REF
K49
VCC3_3[8]
J38
VCC3_3[9]
L38
VCC3_3[10]
M36
VCC3_3[11]
N36
VCC3_3[12]
P36
VCC3_3[13]
U35
VCC3_3[14]
AD13
3062mA
31mA
VCCSATAPLL[1]
VCCSATAPLL[2]
D
+3VALW
C321
0.1U_0402_16V4Z
2
2
1
1
C325
0.1U_0402_16V4Z
+3VALW +5VALW
D16
R344
100_0402_1%
+3VS
2
C326
1
1U_0402_6.3V4Z
D17
CH751H-40PT_SOD323-2
+PCH_VCC5REF
+PCH_VCC5REF
R346
C
100_0402_1%
1
+3VS
2
+5VS
1
C447
22U_0805_6.3V6M
AD38
1U_0402_6.3V4Z
2
2
2
Near V39
1
DCPSUSBYP
1
C318
1U_0402_6.3V4Z
320mA
2
2
2
VCCLAN[2]
Y20
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
C316
1
If two VccME rails can be
combined, only total 2 x 22 µF and
2 x 1 µF caps are necessary
1
C322
22U_0805_6.3V6M
AF24
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
1
1
1
C391
22U_0805_6.3V6M
VCCLAN[1]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
3062mA
2
+1.05VS
AF23
52mA
1
+1.05VS
V24
V26
Y24
Y26
2
Near AD38
VCCACLK[2]
USB
1 +TP_PCH_VCCDSW
0.1U_0402_16V4Z
2
C320
VCCACLK[1]
AP53
PCI/GPIO/LPC
VccLAN may be grounded if Intel LAN is disabled
AP51
1
U11J
D
2
CH751H-40PT_SOD323-2
4
Clock and Miscellaneous
5
C330
1U_0402_6.3V4Z
C333
0.1U_0402_16V4Z
1
+3VS
2
C337
1
0.1U_0402_16V4Z
AK3
AK1
+1.05VS
2
0.1U_0402_16V4Z
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
U20
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
+3VS
1
C344
2
0.1U_0402_16V4Z
+VTT
Remove HDA power rail to +1.5V
1
C345
1
C346
1
C347
2
4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C351
2
0.1U_0402_16V4Z
375mA
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
VCCIO[9]
196mA VCCVRM[4]
AT20
VCCIO[10]
AH19
VCCIO[11]
AD20
VCCIO[12]
AF22
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
AD19
AF20
AF19
AH20
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
AB19
AB20
AB22
AD22
SATA
1
C343
163mA
P18
PCI/GPIO/LPC
+3VALW
3062mA
> 1mA
AT18
V_CPU_IO[1]
AU18
V_CPU_IO[2]
CPU
B
AH22
1849mA
VCCRTC
1
C348
1
C349
2
1U_0402_6.3V4Z
2mA
HDA
A12
A
RTC
+RTCVCC
6mA
IBEXPEAK-M QV20 A0_FCBGA1071
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
HM55R1@
B
+PCH_VRM
+1.05VS
1
2
+1.05VS
AA34 +PCH_VCCME1
Y34 +PCH_VCCME2
Y35 +PCH_VCCME3
AA35 +PCH_VCCME4
L30
+VCC_HDA
1
2
2
0.1U_0402_16V4Z
C342
1U_0402_6.3V4Z
R351
R352
R353
R354
1
1
1
1
2
2
2
2
R356 1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2 0_0402_5%
1U_0402_6.3V4Z
Remove VCCSUSHDA can be
either 1.5V or 3.3V
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
+3VALW
A
C350
3
2
Title
PCH POWER-2
Size Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
23
of
45
5
4
3
2
1
U11I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
D
C
B
A
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
U11H
VSS[0]
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
IBEXPEAK-M QV20 A0_FCBGA1071
HM55R1@
D
C
B
HM55R1@
Compal Electronics, Inc.
Compal Secret Data
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
A
Security Classification
IBEXPEAK-M QV20 A0_FCBGA1071
AB16
4
3
2
Title
PCH-GND
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
24
of
45
5
4
3
2
SATA HDD Conn.
+5VS
1.2A
1
SATA ODD Conn
Place closely JHDD SATA CONN.
1
C356
10U_0805_10V4Z
2
C357
0.1U_0402_16V4Z
2
1
C358
0.1U_0402_16V4Z
2
1
C359
0.1U_0402_16V4Z
JODD @
2
D
SSD HDD need 400mA for 3V(PHISON)
+3VS
+3VS rail reserve for SSD
1
2
1
1
C363
10U_0805_10V4Z
@
2
C364
0.1U_0402_16V4Z
@
1
2
C365
0.1U_0402_16V4Z
@
1
2
C366
0.1U_0402_16V4Z
@
15
14
GND
GND
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_PTX_C_DRX_P4
SATA_PTX_C_DRX_N4
C378 1
C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P4 16
SATA_PTX_DRX_N4 16
SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
C376 1
C375 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_C_DTX_N4 16
SATA_PRX_C_DTX_P4 16
D
+5VS
SANTA_206401-1_RV
JHDD @
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P1 16
SATA_PTX_DRX_N1 16
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_C_DTX_N1 16
SATA_PRX_C_DTX_P1 16
+5VS
C
24
23
GND
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Place components closely ODD CONN.
1.1A
1
+3VS
2
1
1
C354
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
C352
10U_0805_10V4Z
1
C353
2
1
C355
0.1U_0402_16V4Z
2
C360
0.1U_0402_16V4Z
C
+5VS
SANTA_191201-1
this is temp. footprint
USB Conn. (2 Port)
Reserve for EMI request
@ R73
1
1.4A
31
USB_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
20
+USB_VCCA
USB20_N0
1
1
USB20_N0_R
2
2
@ 2
C361
8
7
6
5
RT9715BGS_SO8
1
W=60mils
W=60mils
C19
1
1000P_0402_50V7K
20
USB20_P0
4
4
USB20_P0_R
3
3
2
WCM-2012-900T_0805
1
C18
220U_6.3V_M
2
For EMI request
U48
1
2
3
4
L53
W=60mils
+USB_VCCA
USB_OC#0 20,31
@ R86
1
C21
1
0.1U_0402_16V4Z
C20
2
1
0_0402_5%
2
C362
4.7U_0805_10V4Z
2 @
2
USB-LIGHT1
JUSB1
1000P_0402_50V7K
1
2
3
4
USB20_N0_R
USB20_P0_R
Reserve for EMI request
@
GND
GND
GND
GND
JUSB2
1
2
3
4
USB20_N1_R
USB20_P1_R
VCC
DD+
GND
@
GND
GND
GND
GND
5
6
7
8
ALLTOP C107L8-10405-L
2
D7@
USB-LIGHT2
1000P_0402_50V7K
5
6
7
8
ALLTOP C107L8-10405-L
0_0402_5%
2
3
@ R88
1
VCC
DD+
GND
1
0.1U_0402_16V4Z
C22
2
1
3
+5VALW
+USB_VCCA
+
W=80mils
B
0_0402_5%
2
2
B
D8@
USB20_N1
1
20
USB20_P1
4
PJDLC05_SOT23-3
1
2
2
USB20_N1_R
4
3
3
USB20_P1_R
PJDLC05_SOT23-3
@ R87
1
1
WCM-2012-900T_0805
A
0_0402_5%
2
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
2011/06/21
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
A
1
L54
20
3
2
Title
SATA-HDD/ODD/USB
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
25
of
45
5
4
3
2
1
For EMI request
1
@ CC2
@ RC6
2
100P_0402_50V8J
CLK_48M_CR
1
10_0402_5%
2
@ CC10
1
10P_0402_50V8J
2
D
D
RC2
6.19K_0402_1%
2
1
20
20
+3VS_CR
RC3
0_0603_5%
USB20_N10
USB20_P10
USB20_N10
USB20_P10
+3VS_CR
+VCC_3IN1
V1_8
1 CC3
0.1U_0402_16V4Z
1
CC7
1U_0402_6.3V4Z
4.7U_0805_10V4Z
2
2
SDW P_MSCLK
2
SD_DATA1
SD_DATA0
1
CC4
1
REFE
2
3
DM
DP
4
5
6
3V3_IN
CARD_3V3
V18
7
XD_CD#
8
9
10
11
12
25
CC3, CC4, CC5, CC6,
CC7, RC2, RC3, UC1
form CARD@ to mount
SP1
SP2
SP3
SP4
SP5
GPIO0
17
CLK_IN
24
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
EPAD
+3VS
UC1
0620 --> remove CR_LED#
CLK_48M_CR
< 48MHz >
CLK_48M_CR 13
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
0620 --> remove CARD-RADER LED
SDCMD
MS_DATA2_SDCLK
SDCD#
RTS5137-GR_QFN24_4X4
0715 --> change P/N to RTS5137 (SA000043500)
C
C
< 2 in 1 Card Reader >
0624 --> change CARDREADER conn.
JREAD @
D3 1
CMD 2
VSS1 3
VDD 4
CLK 5
VSS2 6
D0
D1
D2
WP
CD
7
8
9
10
11
GND1
GND2
GND3
GND4
12
13
14
15
MS_DATA1_SD_DATA3
SDCMD
+VCC_3IN1
MS_DATA2_SDCLK
1
SD_DATA0
SD_DATA1
SD_DATA2_MS_DATA5
SDW P_MSCLK
SDCD#
2
CC6
0.1U_0402_16V4Z
1
2
CC5
1U_0402_6.3V4Z
B
B
TAITW _PSDAT3-09GLAS1N14N
For EMI request
@ RC4
MS_DATA2_SDCLK
10_0402_5%
2
@ CC8
1
10_0402_5%
2
@ CC9
1
@ RC5
SDW P_MSCLK
1
10P_0402_50V8J
2
1
10P_0402_50V8J
2
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
RTS5137 2in1 Card Reader
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
26
of
45
PCIe Mini Card-WLAN/WiMax
Slot#1 Half PCIe Mini Card-WLAN/WiMax
BT_CRTL
HI
LO
BT_PWR#
LO
HI
**If +3V_WLAN is +3VS, please
remove D24.
BT_CTRL
17 CLKREQ_WLAN#
17
17
17 PCIE_PRX_WLANTX_N2
17 PCIE_PRX_WLANTX_P2
17 PCIE_PTX_C_WLANRX_N2
17 PCIE_PTX_C_WLANRX_P2
D24 @
CH751H-40PT_SOD323-2
21
BT_PWR#
WLAN/ WiFi
BT_CTRL
2
2
G
Q36
BT@
1
1
D
3
31,34,41 SUSP#
S 2N7002_SOT23-3
CLK_WLAN#
CLK_WLAN
+3V_WLAN
31
31
E51_TXD
E51_RXD
1
1R16
R17
Debug card using
2
0_0402_5%
2
0_0402_5%
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
+3VALW
+3VS
2
@ PJ27 2
1
1 JUMP_43X79
2
@ PJ26 2
1
1 JUMP_43X79
+3V_WLAN
Short PJ27 for WiFi(WLAN)/WiMax combo module
Short PJ26 for WiFi(WLAN) module only.
PLT_RST#
WL_OFF# 31
PLT_RST# 20,28,31,32
+1.5VS
PM_SMBCLK 11,12,13,17
PM_SMBDATA 11,12,13,17
USB20_N13 20
USB20_P13 20
For SED
0.1U_0402_16V4Z
1
1
CM7
WiMax
CM8
2
0.01U_0402_25V7K
1
@
C254
47P_0402_50V8J
2
4.7U_0805_10V4Z
CM9
2
+3V_WLAN
For SED
0.1U_0402_16V4Z
1
1
CM1
CM2
2
0.01U_0402_25V7K
1
1
Disable
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
@
C253
47P_0402_50V8J
2
4.7U_0805_10V4Z
CM3
2
2
Enable
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
BT
on module
+3V_WLAN
2 A
2
JWLAN
WLAN&BT Combo module circuits
BT
on module
+1.5VS
1 A
@ FOX_AS0B226-S40N-7F
Compal Secret Data
Security Classification
Issued Date
2010/06/21
Deciphered Date
Compal Electronics, Inc.
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCIe-WLAN
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
27
of
45
A
B
C
3/19 --> Change JLAN for don't support LAN LED fuction
--> Pin40, 37 change to NC Pin
UL1
17 PCIE_PRX_C_LANTX_P1
CL1
1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1
22
HSOP
17 PCIE_PRX_C_LANTX_N1
CL2
1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1
23
HSON
17
18
17 PCIE_PTX_C_LANRX_P1
17 PCIE_PTX_C_LANRX_N1
D
LED3/EEDO
LED1/EESK
LED0
31
37
40
EECS/SCL
EEDI/SDA
30
32
HSIP
HSIN
0715 --> LL1, CL13, CL9, LL3, CL28,
CL29 are unmount for RTL8105E-VC
RL19
0_0402_5% 16
1
RL3
@
2 PCH_W AKE#
100K_0402_5%
18
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
RL2
RL1
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
1 10K_0402_5%
1 10K_0402_5%
2
2
1
0.1U_0402_16V4Z
43
CKXTAL1
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
DVDD33
DVDD33
27
39
+3V_LAN
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
+3V_LAN
33
ENSWREG
EVDD10
21
+LAN_EVDD10
0.1U_0402_16V4Z
34
35
VDDREG
VDDREG
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
0.1U_0402_16V4Z
REGOUT
36
1 RL22
RL22 need always pull-high
for RTL8105E Efuse mode
2 1K_0402_5%
ENSW REG
+LAN_VDDREG
+3VS
1
RL5
2
2.49K_0402_1%
@
46
RSET
24
49
GND
PGND
+LAN_VDD10
1
2
CL4
2
CL5
2
CL6
2
CL7
1
1
+LAN_EVDD10
2
0_0603_5%
1
LL2
CL18
1U_0402_6.3V4Z
1
2
2
CL17
0.1U_0402_16V4Z
1
CL19,CL20,CL21,CL22 close to
Pin 3,13,29,45
+LAN_VDD10
0.1U_0402_16V4Z
Close to Pin 21
0.1U_0402_16V4Z
+3V_LAN
1
2
CL19
2
CL20
2
CL21
2
CL22
1
1
1
+LAN_VDDREG
2
0_0603_5%
+LAN_REGOUT
2
CL10
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+LAN_VDD10
1
1
LAN_X2
PCH_W AKE#
1
2
0.1U_0402_16V4Z
CL9 @
0.1U_0402_16V4Z
LAN_X1
ISOLATEB
2
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
2
REFCLK_P
REFCLK_N
+3V_LAN
RL6
1K_0402_1%
0.1U_0402_16V4Z
1
Layout Note: LL1 must be
within 200mil to Pin36,
@CL13
@
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
+LAN_REGOUT: Width =60mil
PERSTB
PCH_W AKE#
2
+3V_LAN
LL1 @
19
20
CLK_LAN
CLK_LAN#
+3V_LAN
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
+LAN_VDD10
25
20,27,31,32 PLT_RST#
17
17
CLKREQB
C10,CL4,CL5,CL6,CL7 close to
Pin 27,39,12,47,48
LL1,CL13 will be changed to
2.2uH&4.7uF after EVT test
1
17 CLKREQ_LAN#
E
1
LL3 @
@CL28
@
CL28
4.7U_0603_6.3V6K
RTL8105E-GR QFN _6X6
2
1
2
2
CL29 @
0.1U_0402_16V4Z
1
ISOLATEB
0715 --> change P/N to SA00003PO20 (RTL8105E-VC )
RL7
15K_0402_5%
+3V_LAN
ISOLATEB
RL10
@ 0_0402_5%
LAN Conn.
W OL_EN# 31,34
4/2->remove RL8, RL9, CL11
@ RL4
0_0402_5%
RL11
0_0402_5%
W OL_EN
JLAN @
YL1
31
ENSW REG
LAN_X1
1
2
LAN_X2
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
RJ45_MIDI1+
3
PR2+
RJ45_MIDI0-
2
PR1-
RJ45_MIDI0+
1
PR1+
25MHZ_20PF_7A25000012
RL23
0_0402_5%
Add RL10 for +3V_LAN power enable signal
Add RL11 for wake on LAN function enable signal
1
CL26
27P_0402_50V8J
2
1
CL27
27P_0402_50V8J
RJ45_MIDI1-
2
3
0715 --> RL4 is unmount,
RL23 mount for
RTL8105E-VC
3/29 --> swap Line and PHY signal
3
SHLD1
9
SHLD2
10
UL3
SANTA_130452-C
LAN_MDI1LAN_MDI1+
1
2
3
4
5
6
7
8
LAN_MDI0LAN_MDI0+
Place these components
colsed to LAN chip
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI1RJ45_MIDI1+
RJ45_MIDI0RJ45_MIDI0+
CL42
2
1000P_0402_50V7K
1
CL41
2
1000P_0402_50V7K
1
1
RL15
2
75_0402_1%
1
RL13
2
75_0402_1%
RJ45_GND
RJ45_GND
1
CL36
LANGND
2 1000P_1808_3KV7K
1
LFE8456E-R
1
2
TD+
TDCT
NC
NC
CT
RD+
RD-
2
1
CL37
0.1U_0402_16V4Z
2
CL38
4.7U_0603_6.3V6K
CL34
0.1U_0402_25V6
4
4
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
Compal Electronics, Inc.
RTL8105E 10/100 LAN
Size Document Number
Custom
Date:
Rev
0.2
PWWAA LA6842P M/B
W ednesday, July 28, 2010
Sheet
E
28
of
45
A
B
C
D
Pin36
Codec
+PVDD1
1
DVDD
Ext. Mic
30
30
4.7U_0805_10V4Z
MIC1_R_L
MIC1_R_R
4.7U_0805_10V4Z
2
2
1 CA23
1 CA29
2
14
15
LINE2_L
LINE2_R
SPK_OUT_R+
SPK_OUT_R-
45
44
21
22
MIC1_L
MIC1_R
HP_OUT_L
HP_OUT_R
32
33
MIC2_L
MIC2_R
2
GPIO0/DMIC_DATA
3
GPIO1/DMIC_CLK
4
PD#
11
16 AZ_RST_HD#
MONO_IN
2
100P_0402_50V8J
SENSE_A
1
2
CA15
2.2U_0603_6.3V4Z
+MIC1_VREFO_L
3
12
place close to chip
30
30
SPKR+
SPKR-
30
30
RA5
75_0402_1%
HP_L
30
HP_R
30
Beep sound
16
BCLK
6
AZ_BITCLK_HD
16
SDATA_OUT
5
SDATA_IN
8
AZ_SDOUT_HD
EAPD
47
SPDIFO
48
MONO_OUT
20
MIC2_VREFO
29
MIC1_VREFO_R
LDO_CAP
30
28
SENSE A
SENSE B
1
33_0402_5%
AZ_SDIN0_HD
2
EC Beep
31
16
@
2
1
R391 10_0402_5%
AZ_BITCLK_HD
2
@ C24
1
10P_0402_50V8J
@
2
1
R402 10_0402_5%
AZ_RST_HD#
1
+MIC1_VREFO_R CA28 10U_0805_10V4Z
1
2
CBP
CBN
VREF
27
AC_VREF
31
MIC1_VREFO_L
JDREF
19
AC_JDREF2 RA9
43
42
49
7
PVSS2
PVSS1
DVSS2
DVSS1
CPVEE
34
1
CA14
AVSS1
AVSS2
26
37
1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
DGND
CA50 1
2 0.1U_0603_50V7K
ALC259Q PN IS NOT READY
4
CA16
10U_0805_10V4Z
2
2 @
0.1U_0402_16V4Z
Place close to chip
3
ALC259-GR_QFN48_7X7
place close to chip
2
0_0603_5%
+MIC1_VREFO_R
AGND
Codec Signals
1
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
30
MIC_SENSE
2
RA10
1
20K_0402_1%
@
CA37
1U_0402_6.3V4Z
2
@
CA36
1U_0402_6.3V4Z
0618 --> remove +MIC2_VREFO
for analog IntMIC
For EMI
13 INT_MIC_CLK
30
NBA_PLUG
RA21
39.2K_0402_1%
0620 --> remove RA13 for SENSE_B
PORT-E (PIN 14, 15)
Issued Date
RA41
INT_MIC_CLK_R
FBMA-10-100505-301T
CAM@
1
CA30
27P_0402_50V8J
@
2
2010/06/21
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
4
Compal Secret Data
Security Classification
A
1
SENSE_A
(PIN 48)
39.2K
+MIC1_VREFO_L
place close to chip
Function
39.2K
5.1K
CA18
0.1U_0402_16V4Z
1
CA17
2
SENSE A
2
1 20K_0402_1%
2
2.2U_0603_6.3V4Z
CA48 1
Impedance
MONO_IN
0.1U_0402_16V4Z
RA12
10K_0402_5%
For EMI, place near codec
0618 --> remove +MIC2_VREFO for analoh IntMIC
35
CA13
1
2
RA8
1
2
47K_0402_5%
16,19 PCH_SPKR
1
10P_0402_50V8J
2 0.1U_0603_50V7K
Sense Pin
RA7
1
2
47K_0402_5%
EC_BEEP#
PCI Beep
16
2
@ C23
36
ANALOG
Pin12
DIGITAL
(Include Themal PAD)
AZ_SYNC_HD
2
RA6
Pin1
Moat
SPKL+
SPKL-
75_0402_1%
AZ_SDIN0_HD_R
Pin13
1
CA6
RA4
CA47 1
1
RA18
1
CA5
10
PCBEEP
18
1
CA4
SYNC
RESET#
13
0620 --> remove SENSE_B
EC_MUTE#
1
RA45
2
40
41
INT_MIC_CLK_R
31 EC_MUTE#
2
4.7K_0402_5%
1
SPK_OUT_L+
SPK_OUT_L-
INT_MIC_DATA
1
CA3
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
LINE1_L
LINE1_R
Int. Mic
1
CA12
2
2
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VS
0_0603_5%
Pin48
UA1
23
24
16
17
13 INT_MIC_DATA
2
10U_0805_10V4Z
68 mA
35mA for 3.3V level
ALC259-GR
0.1U_0402_16V4Z
+5VS
1
1
CA62
@
@
CA58
1
2
@
0.1U_0402_16V4Z
2
+AVDD
RA11
2
1
0_0603_5%
@
CA63
2
1
CA7
10U_0805_10V4Z
2
place close to chip
Pin39
2
10U_0805_10V4Z
1
1
38
1
35 mA
25
CA8
2
1
0.1U_0402_16V4Z
2
1
0_0603_5%
Pin24
Pin38
place close to chip
AVDD2
+3VS
Pin37
+5VS
CA43
2
10U_0805_10V4Z
+PVDD2
1
CA61
AVDD1
RA1
2
+3VS_DVDD
2
46
10U_0805_10V4Z
2
@
1
39
CA1
PVDD2
1
CA2
Del RA20 with connect to +1.5VS
9
1
PVDD1
2
RA19 0_0603_5%
DVDD_IO
1
JA1
JUMP_43X39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CA44
2
1
0_0603_5%
CA56
2
+DVDD_IO
+3VS
0.1U_0402_16V4Z
1
1
CA57
JA1 place on +5vs source side
Pin25
RA2
600 mA
C
Title
HDA CODEC ALC259-GR
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
D
Sheet
29
of
45
5
4
3
2
1
Speaker Connector
placement near Audio Codec
D
D
29
SPKL+
SPKL+
1
RA26
2
0_0603_5%
SPK_L1
2
RA27
29
SPKL-
SPKL-
1
2
0_0603_5%
@ DA4
CA22 @
470P_0402_50V8J 2
1
CA24
1U_0402_6.3V4Z
2
@
1
CA21 @
470P_0402_50V8J
1
SPK_L2
3
JSPK @
SPK_L1
SPK_L2
SPK_R1
SPK_R2
1
2
3
4
@ DA5
RA28
29
SPKR+
SPKR+
1
2
0_0603_5%
RA29
29
C
SPKR-
SPKR-
1
2
0_0603_5%
PJDLC05_SOT23-3
2
1
PJDLC05_SOT23-3
3
1
2
3
4
ACES_85204-0400N
1
SPK_R1
2
2
CA25 @
470P_0402_50V8J 2
1
CA27
1U_0402_6.3V4Z
2
@
1
CA26 @
470P_0402_50V8J
1
SPK_R2
place near JSPK conn.
C
Ex.MIC JACK
JEXMIC
MIC1_L_L
1
CA9
100P_0402_50V8J
2
@
B
3
6
2
1
1
DA6 @
CA10
100P_0402_50V8J
2 @
1
2
6
3
MIC1_L
MIC1_L_R
LA6 1
2
KC FBM-L11-160808-121LMT 0603
LA8 1
2
KC FBM-L11-160808-121LMT 0603
4
MIC1_R
5
4
29 MIC_SENSE
7
8
GND
GND
5
AGND
10
9
8
7
Ext.MIC/LINE IN
FOX_JA63331-B39S4-7F
@
2
CA11
100P_0402_50V8J
2
@
1
DA7 @
CA19
100P_0402_50V8J
2 @
2
1
2
6
3
HP_L_R
1
4
HP_L
3
6
2
1
5
29
4
HP_R_R
LA9 1
2
KC FBM-L11-160808-121LMT 0603
LA101
2
KC FBM-L11-160808-121LMT 0603
7
8
GND
GND
HP_R
+MIC1_VREFO_R
MIC1_R
B
MIC1_L
RA25 1
2
2.2K_0402_5%
+MIC1_VREFO_L
Int. Mic
JLINE
5
AGND
NBA_PLUG
2
1
1K_0402_5%
RA24
29 MIC1_R_L
Head Phone JACK
29
RA22 1
2
2.2K_0402_5%
3
PJDLC05_SOT23-3
29
RA23
1K_0402_5%
2
1
29 MIC1_R_R
1
0618 --> remove Analog IntMIC, and change to DIGITAL MIC
10
9
8
7
FOX_JA63331-B39S4-7F
@
1
3
PJDLC05_SOT23-3
A
A
2010/06/21
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/21
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
HDA CODEC ALC259-GR
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
30
of
45
5
4
3
2
1
+3VL
+3VL
1
1
1000P_0402_50V7K
U19
for EMI request
21
GATEA20
21 KB_RST#
16,32 SERIRQ
16,32 LPC_FRAME#
16,32 LPC_AD3
16,32 LPC_AD2
16,32 LPC_AD1
16,32 LPC_AD0
1
CLK_PCI_EC
2
R377
@ 10_0402_5%
1
20 CLK_PCI_EC
20,27,28,32 PLT_RST#
C443
@ 22P_0402_50V8J
+3VL
2
21
R378
47K_0402_5%
2
1
2
C444
ECRST#
EC_SCI#
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
12
13
37
20
38
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
1
0.1U_0402_16V4Z
1
R380
1
R382
2
47K_0402_5%
2
47K_0402_5%
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
KSO1
KSO2
to avoid EC entry ENE test mode
2
C455
C
2
C456
PLT_RST#
1 @
0.1U_0402_16V4Z
KB_RST#
1
0.1U_0402_16V4Z
32
KSI[0..7]
32
KSO[0..17]
KSI[0..7]
KSO[0..17]
For ESD
+3VS
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
36
36
17
17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PS2
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
THM_ALT#
6
14
15
16
17
18
PCH_SUSPW RDN 19
25
FAN_SPEED1
28
29
E51_TXD
30
E51_RXD
31
ON/OFFBTN#
32
34
NUM_LED#
36
CRY1
CRY2
R389
2CRY2
@ 10M_0402_5%
OSC
NC
@
2
EC_CLK
2
0_0402_5%
R624
100K_0402_5%
@
C450
18P_0402_50V8J
OSC
NC
Y4
3
2
4
1
1
1
2
18P_0402_50V8J
@
C449
18
1
R103
2 0_0402_5%
2 0_0402_5%
122
123
1
2
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
Interface
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
VGATE
W OL_EN#
PW RME_CTRL#
LID_SW #
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
@
C480
ACOFF
35,37
BATT_TEMPA 36
ADP_I
ADP_V
ADP_I
ADP_V
Remove CEC_INT# pull high
37
37
VTTP_EN 39
EN_DFAN1 6
IREF
37
CHGVADJ 37
SPI Flash ROM
SM Bus
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
2
100K_0402_5%
+5VS
EC_MUTE# 29
USB_EN# 25
TP_CLK
TP_CLK
TP_DATA
100
101
102
103
104
105
106
107
108
1
R337
TP_CLK 33
TP_DATA 33
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW _LED#
VGATE
18,42
W OL_EN# 28,34
PW RME_CTRL# 16
LID_SW # 32
2
4.7K_0402_5%
2
4.7K_0402_5%
1
R383
2
47K_0402_5%
SYSON
1
R5
2
4.7K_0402_5%
VR_ON
1
R462
2
10K_0402_5%
+3VALW
C
LID_SW #
EC_SI_SPI_SO 32
EC_SO_SPI_SI 32
SPI_CLK 32
SPI_CS# 32
FSTCHG 37
BATT_FULL_LED# 33
CAPS_LED# 32
BATT_CHG_LOW _LED# 33
0621->remove PWR_ON_LED#
SYSON
VR_ON
ACIN_D
1
R379
1
R381
TP_DATA
SYSON
VR_ON
40
42
For prevent leakage for CPU_CORE
EC_RSMRST#
EC_LID_OUT#
EC_ON
PM_PW ROK
BKOFF#
W L_OFF#
EC_RSMRST# 18
EC_LID_OUT# 17
EC_ON
33,38
PM_PW ROK 18
BKOFF#
13
W L_OFF# 27
R341 330K_0402_5%
1
2
+3VL
D21
EC_SEL
18
2
ACIN_D
1
ACIN
18,37
B
CH751H-40PT_SOD323-2
GPI
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
XCLK1
XCLK0
PM_SLP_S4#
EC_ENBKL
PM_SLP_S4# 18
EC_ENBKL 19
SUSP#
PBTN_OUT#
USB_OC#0
SUSP#
SUSP#
27,34,41
PBTN_OUT# 18
USB_OC#0 20,25
1
R423
2
10K_0402_5%
+EC_V18R
+3VALW
C448
4.7U_0805_10V4Z
KB926QFE0_LQFP128_14X14
R435
100K_0402_5%
@
EC_SEL
R436
100K_0402_5%
For EC Crystal cost down
EC SEL
EC Version
High
KB926D3
Low
KB926E0
1
1
@ R104 1
@ R108 1
2
CRY1
E51_TXD
E51_RXD
ON/OFFBTN#
PW R_LED#
NUM_LED#
VTTP_EN
EN_DFAN1
IREF
CHGVADJ
GND
GND
GND
GND
GND
27
27
33
33
32
68
70
71
72
ACOFF
2
6 FAN_SPEED1
E51_TXD
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
remove SM_SENSE
EC_BEEP# 29
18P_0402_50V8J
100K_0402_5%
1
2
1
R342
B
BATT_TEMPA
11
24
35
94
113
18 PCH_SUSPW RDN
63
64
65
66
75
76
EC_BEEP#
SPI Device Interface
2.2K_0804_8P4R_5%
18 PM_SLP_S3#
18 PM_SLP_S5#
21
EC_SMI#
21
THM_ALT#
for Wake on LAN 28
W OL_EN
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
PWM Output
RP7
1
2
3
4
+3VL
remove KB LED
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
2
100P_0402_50V8J
2
100P_0402_50V8J
D
21
23
26
27
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
VTTP_EN
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
1
C445
1
C446
0.1U_0402_16V4Z
AD
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
+3VL
ACIN_D
2
2
2
0.1U_0402_16V4Z
C441
1000P_0402_50V7K
1
2
C440
AVCC
D
2
C439
VCC
VCC
VCC
VCC
VCC
VCC
0.1U_0402_16V4Z
C438
67
C437
BATT_TEMPA
C442
1
2
AGND
C436
2
69
1
0.1U_0402_16V4Z
1
2
9
22
33
96
111
125
0.1U_0402_16V4Z
1
1
32.768KHZ_12.5PF_Q13MC14610002
A
A
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Remove PM_SLP_S4#/S5# AND Gate
5
Compal Electronics, Inc.
Compal Secret Data
Security Classification
4
3
2
Title
ENE-KB926 RevD2
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
31
of
45
Lid SW
SPI Flash (256KB)
LPC Debug Port
Please place the PAD under DDR DIMM.
+3VS
H7
+3VALW
+3VL
U21
APX9132ATI-TRL_SOT23-3
31 SPI_CS#
31
SPI_CLK
SPI_CLK
3
W
7
HOLD
1
S
6
C
5
31 EC_SO_SPI_SI
2
VSS
4
1
2
VDD
VOUT
C453
0.1U_0402_16V4Z
16,31
3
LID_SW #
SERIRQ
31
1
C452
10P_0402_50V8J
1
2
R392 0_0402_5%
Q
4
PLT_RST# 20,27,28,31
3
LPC_AD2 16,31
16,31
LPC_AD3
8
16,31
LPC_AD1
9
2
LPC_AD0 16,31
10
1
CLK_PCI_DDR
2
16,31 LPC_FRAME#
D
5
7
20
2
2
VCC
GND
0.1U_0402_16V4Z
U22
8
1
C451
20mils
1
6
2
EC_SI_SPI_SO 31
DEBUG_PAD
@
R393
22_0402_5%
1
MX25L2005CMI-12G SOP 8P
SPI_CLK
1 R394 @2
10_0402_5%
2
1
C454
2
@ 10P_0402_50V8J
1
reserve for EMI, close to U22
C457
22P_0402_50V8J
reserve for EMI
KEYBOARD CONN.
please close to JKB
KSI[0..7]
KSO[0..17]
KSI[0..7]
31
KSO16
KSO[0..17] 31
JKB @
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88170-3400
1
C401
1
C402
KSO2
1
C404
KSO1
1
C405
KSO0
1
C406
KSO4
1
C407
KSO3
1
C408
KSO5
1
C409
KSO14
1
C410
KSO6
1
C411
KSO7
1
C412
KSO13
1
C413
KSO8
1
C415
KSO9
1
C416
KSO10
1
C417
KSO11
1
C418
KSO12
1
C419
KSO15
1
C420
KSI7
1
C421
KSI2
1
C422
KSI3
1
C423
KSI4
1
C424
KSI0
1
C425
KSI5
1
C427
KSI6
1
C429
KSI1
1
C431
CAPS_LED#
1
C433
NUM_LED#
1
C435
KSO17
JKB34
KSO16
1
2
R372 300_0402_5%
+3VS
KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R376 300_0402_5%
NUM_LED#
+3VS
CAPS_LED# 31
NUM_LED# 31
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
SPI ROM/TP/KB/Debug
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
32
of
45
5
4
3
Power Button
2
R396
10K_0402_5%
D
S 2N7002_SOT23-3
LEFT
SW_L
SW1
1
1
SW2
1
3
2
4
6
5
TOP side
1
SMT1-05_4P
2
ON/OFFBTN#
6
5
RIGHT
C458
0.1U_0402_25V6
@
SW_R
PWR/B to MB Conn.
TP_CLK
TP_DATA
SW_L
SW_R
2
SW4
1
3
2
4
6
5
1
2
ON/OFFBTN#
1
2
3
4
5
6
7
8
+5VS
31
31
3
1
2
3
4
5
6
GND
GND
D
ACES_85201-06051
D19 @
AZ5125-02S.R7G_SOT23-3
SMT1-05_4P
0620->change JTOUCH connector
D20 @
AZ5125-02S.R7G_SOT23-3
D83 @
AZ5125-02S.R7G_SOT23-3
1
SMT1-05_4P
3
JPOWER @
1
1
2 2
3 3
4 4
5
G1
6
G2
For EMI request
3
4
2
3
2
6
5
1
JTOUCH @
4
SMT1-05_4P
ON/OFFBTN# 31
SW3
BTM side
3
1
100K_0402_5%
D
1
TP Button/Conn.
35
2
R395
debug phase using
2
G
Q38
1
EC_ON
2
31,38
+3VL
3
51_ON#
2
1
ACES_85201-0405N
For EMI request
For ESD
Screw Hole
1
H12
H13
H_3P0
@
1
H_3P0
@
C
H_3P0
@
1
H11
H_3P0
@
1
1
1
H10
H_3P0
@
PWR_LED# 31
H26
H17
H_3P0
@
MINI CARD
H21
1
H_4P2x4P7
@
SB
H19
H_3P3
@
1
H_4P2
@
H18
H15
H_3P3
@
H16
H_5P0N
@
1
H20
Vf=1.8V~2.0V
If=5mA(max)
H_1P0N
@
1
CPU
BATT CHARGE/FULL LED
H14
H_2P7N
@
H_5P0N
@
1
1
H_2P7x3P2N
@
1
H1
HT-110UYG5_YELLOW GREEN
1
YG
H9
H_3P0
@
1
2
510_0402_5%
H8
H_3P0
@
1
2
3
1
R397
1
D22
+5VALW
H6
H_3P0
@
1
H5
Vf=1.9V~2.4V
If=5mA
C
1
POWER/SUSPEND LED
D25
2
1
510_0402_5%
A
2
BATT_CHG_LOW_LED# 31
3
BATT_FULL_LED# 31
YG
B
H22
H23
H_4P2x4P7
@
H_4P7
@
1
1
R399
1
+5VALW
B
HT-210UD5-UYG5_AMBER-YEL GRN
For Codec AGND
PCB Fedical Mark PAD
FD1
FD2
@
FD3
@
1
@
1
MDC
FD4
@
1
3G
1
Dummy
ISPD
ZZZ
PJP1
PCB
U11
DC-IN
PCB LA-6842P REV0
PCH
PJP1
45@
PCH
HM55R3@
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
2011/06/21
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PWR BTN/Can. Sensor/TP/LEDs
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
33
of
45
A
B
C
+3VALW TO +3VS
+3VALW
+3VS
D
E
+5VALW TO +5VS
+1.5V to +1.5VS
+5VALW
Vgs=-0V,Id=9A,Rds=18.5mohm
+5VS
+1.5V
4.7U_0805_10V4Z
+1.5VS
4.7U_0805_10V4Z
2
1
FDS6676AS
C469
2
2
R414
820K_0402_5%
1 R411
2
+VSB
220K_0402_5%
3 1
1
R408
470_0805_5%
2
1
Q12A
Q12B
SUSP 5
2
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
4
Q11B
SUSP 5
2
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
2
1U_0402_6.3V4Z
SI4800BDY_SO8
Q11A
1
C464
6
3 1
6
R413
200K_0402_5%
@
470_0805_5%
2
C468
2
1
2
3
4
S
S
S
G
1
2
1
C463
D
D
D
D
1
C467
1
1
+VSB
Q31
8
7
6
5
1
2
1
R407
0.1U_0402_25V6
@
2
1U_0402_6.3V4Z
1 R410
2
47K_0402_5%
SI4800BDY_SO8
C821
2
C470
2
C315
2
4.7U_0805_10V4Z
SUSP
2
5
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
1
1
2
3
4
Vgs=10V,Id=14.5A,Rds=6mohm
1
4
1
Q10B
C292
2
S
S
S
G
C462
1
2
Q10A
1
D
D
D
D
1
2
R412
330K_0402_5%
+VSB
8
7
6
5
C461
0.01U_0402_25V7K
6
C466
1
1
2
2
0.022U_0402_25V7K
4.7U_0805_10V4Z
C465
1 R409
2
47K_0402_5%
+5VS
+3VS
4.7U_0805_10V4Z
1U_0402_6.3V4Z
SI4800BDY_SO8
1
R406
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
1
2
3
4
S
S
S
G
Q30
3 1
1
D
D
D
D
C460
4
8
7
6
5
C459
1
4.7U_0805_10V4Z
470_0805_5%
Q29
1
For EMI request
For EMI request
0715 --> Q31 change to SB548000310 the same as +5VS
+3VALW TO +3V_LAN
For S3 CPU Power Saving
+3VALW
+3VALW
2
1
1
Q48B
2N7002DW -T/R7_SOT363-6
+3V_LAN
1
R169
5,39 VTTPW ROK
2
1
Q48A
2N7002DW -T/R7_SOT363-6
1
@ C479
2
1U_0402_6.3V4Z
0.75VR_EN
2
100K_0402_5%
SUSP
2
5
Q48A,B
R169, R425 form PS@ to mount
2
1
@ C476
4.7U_0805_10V4Z
0.75VR_EN# 41
3
PJ24
JUMP_43X79
@
4
1
1
2
6
2
3
1
@ C474
0.01U_0402_25V7K
@ Q32
AO3413_SOT23
1
1
2
47K_0402_5%
2
R425
100K_0402_5%
G
1
@ R420
W OL_EN#
2
D
28,31
Vgs=-4.5V,Id=3A,Rds<97mohm
@
C471
0.1U_0402_16V7K
S
@
R419
100K_0402_5%
2
2
2
+3VALW
Reserve for EMI test
2
1
C478
0.1U_0402_16V7K
R422
100K_0402_5%
2
9,41
1
SUSP
SUSP
Q5A
2N7002DW -T/R7_SOT363-6
0715 --> change R412 from 470ohm to 47ohm
2
Q5B
2N7002DW -T/R7_SOT363-6
5
SUSP
4
SUSP#
1
27,31,41
R421 form PS@ to mount
R421
47_0805_5%
6
1
@
C475
0.1U_0402_16V7K
+0.75VS
1
2
+5VALW
+5VALW
3
@
C473
0.1U_0402_16V7K
+5VS
1
+3VS
2
3
2
3
4
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Title
DC-DC INTERFACE
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
E
34
of
45
A
B
C
D
VIN
PL1
SMB3025500YA_2P
1
2
PF1
DC301001M80
DC_IN_S1
1
DC_IN_S2
2
1
PC6
100P_0402_50V8J
2
1
2
1
2
PC5
680P_0402_50V7K
@
PC4
1000P_0402_50V7K
2
1
4
PC3
100P_0402_50V8J
-
@ SINGA_2DW -0005-B03
2
-
3
1
2
2
1
+
1
+
1
PC2
680P_0402_50V7K
7A_24VDC_429007.W RML
PC1
1000P_0402_50V7K
PJP1
@
1
2
VIN
PD2
RLS4148_LL34-2
PR10
68_1206_5%
1
2
1K_1206_5%
B+
2
100K_0402_5%
100K_0402_5%
2
2
1
2
1
PR6
2
PR4
PR3
1
2
1K_1206_5%
PC10
0.1U_0603_25V7K
1
VS
1
2
2
1
51_ON#
1
2
1
PC9
0.22U_0603_25V7K
3
LL4148_LL34-2
PR5
PR13
100K_0402_1%
1K_1206_5%
2
PR7
PR15
22K_0402_1%
1 2
100K_0402_5%
1
33
1
PR2
1
PD3
RLS4148_LL34-2
3
2
1
N1
1
1
2
BATT+
2
1K_1206_5%
2
2
VIN
PQ2
TP0610K-T1-E3_SOT23-3
PD1
1
2
PR9
68_1206_5%
2
PQ1
TP0610K-T1-E3_SOT23-3
1
1
1
PreCHG
PR1
PD4
2
+5VALW P
3
38
1
2
2
PQ3
PQ30
3
RB715F_SOT323-3
DTC115EUA_SC70-3
3
ACOFF
31,37
DTC115EUA_SC70-3
3
3
PJ1
+3VALW P
2
2
PJ4
1
1
+3VALW
2
+1.5VP
@ JUMP_43X118
(5A,200mils ,Via NO.= 10)
2
1
1
+5VALW
(5A,200mils ,Via NO.= 10)
2
1
2
1
1
+1.8VS
@ JUMP_43X79
(2A,80mils ,Via NO.= 4)
2
PJ9
1
1
+GFX_CORE
1
2
+3VLP
2
2
1
1
+3VL
@ JUMP_43X39
(100mA,40mils ,Via NO.= 2)
PJ10
2
PJ7
2
2
+1.8VSP
@ JUMP_43X118
OCP(min)=7.9A
2
+1.5V
PJ8
+GFX_COREP
@ JUMP_43X118
+VSBP
1
OCP(min)=9.8A
PJ5
2
PJ3
1
(9A,360mils ,Via NO.= 18)
OCP(min)=7.7A
+5VALW P
2
@ JUMP_43X118
1
1
@ JUMP_43X118
+VSB
(22A,880mils ,Via NO.=44)
@ JUMP_43X39
OCP(min)=26A
(120mA,40mils ,Via NO.= 1)
PJ17
PJ11
4
2
2
1
+0.75VSP
1
2
2
1
1
4
+0.75VS
@ JUMP_43X79
(1.5A,60mils ,Via NO.= 4)
@ JUMP_43X118
PJ13
+VTTP
2
2
1
1
+VTT
Issued Date
(20A,800mils ,Via NO.=40)
Compal Electronics, Inc.
Compal Secret Data
Security Classification
@ JUMP_43X118
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
OCP(min)=27.49A
A
B
C
Title
DCIN / DETECTOR
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
D
35
of
45
A
B
1
C
1
VMB
1
2
10A_125V_451010MRL
BATT+
+3VLP
@ PC18
0.1U_0402_25V6K
PR30
1K_0402_1%
2
1
1
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
1
BATT_S1
1
2
3
4
5
6
7
8
9
PH1 under CPU botten side :
CPU thermal protection at 95degree C
Recovery at 56 degree C
PC16
1000P_0402_50V7K
PC17
0.01U_0402_25V7K
2
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
1
10
11
12
13
PL2
SMB3025500YA_2P
1
2
PF2
2
PJP2
D
2
@ SUYIN_200045MR009G171ZR
VL
1
1
1
PC19
0.1U_0402_16V4Z
PR31
19.6K_0402_1%
2
PR32
6.49K_0402_1%
2
1
+3VLP
2
3
2
PD6
2
PJSOT24C_SOT23-3
3
2
1
PD7
PJSOT24C_SOT23-3
1
PR34
8.66K_0402_1%
PU4
VCC TMSNS1
8
2
GND RHYST1
7
3
OT1 TMSNS2
6
4
OT2 RHYST2
5
2
PR37
100_0402_1%
BATT_TEMPA 31
38
1
1
PR36
100_0402_1%
VS_ON
PH1
100K_0402_1%_NCP15W F104F03RC
2
2
2
2
1
1
1
PR35
1K_0402_1%
2
G718TM1U_SOT23-8
EC_SMB_DA1 31
EC_SMB_CK1 31
PQ4
TP0610K-T1-E3_SOT23-3
3
B+
+VSBP
1
2
PR42
22K_0402_1%
1
2
1
2
2
1
2
@
PC21
0.1U_0603_25V7K
VL
PC20
0.22U_0603_25V7K
3
2
1
PR41
100K_0402_1%
3
@
PR44
0_0402_5%
2
1
1
D
3
POK
S
PQ5
SSM3K7002FU_SC70-3
2
G
2
1
18,38
@ PC22
.1U_0402_16V7K
1
PR43
100K_0402_1%
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
BATTERY CONN / OTP
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
D
36
of
45
CELLS
CSOP
21
5
ICOMP
CSIN
20
VCOMP
CSIP
19
ICM
PHASE
18
LX_CHG
VREF
UGATE
17
DH_CHG
1
4
2
4.7U_0805_25V6-K
PC26
1
4.7U_0805_25V6-K
2
1
1
1
1
PL3
10UH_MSCDRI-104A-100M-E_4.6A_20%
CHG
1
2
10
16
VDDP
15
VADJ
LGATE
14
GND
PGND
13
ACLIM
2
PR70
20K_0402_1%
11
12
1
2
AO4466L_SO8
PD12
RB751V-40TE17_SOD323-2
6251VDDP
DL_CHG
PQ19
26251VDD
4
1
BOOT
PC40
0.1U_0603_25V7K
BST_CHGA 2
1
PR71
4.7_0603_5%
PC45
4.7U_0805_6.3V6K
1
2
1
PR63
0.02_1206_1%
4
2
3
BATT+
PC41
10U_1206_25V6M
2
1
6251aclim
CHLIM
PR67
0_0603_5%
BST_CHG 1
S
2
2
8
9
PR68
75K_0402_1%
6251VREF 1
2
2
3
5
6
7
8
1
2
1
PQ16
2N7002W -T/R7_SOT323-3
3
2
1
6251VREF
D
2
G
AO4466L_SO8
4
@ PC43
@ PR65
680P_0603_50V8J 4.7_1206_5%
3
ACPRN
PQ17
PR61
2.2_0603_1%
1
1
2
PC39
.1U_0402_16V7K
PR69
120K_0402_1%
CSOP
5
6
7
8
ADP_I
PR66
154K_0402_1%
2
1
PQ20
DTC115EUA_SC70-3
2
6
PR62 47K_0402_1%
2
7
1
BATT_ON
CSON
PC32
0.047U_0603_16V7K
1
2
PR58
20_0603_5%
2
1
PR59
PC37
20_0603_5%
0.1U_0603_25V7K
1
2
PC107
10U_1206_25V6M
2
1
4
38
PR57
20_0603_5%
1
2
PC42
10U_1206_25V6M
2
1
CSON
ACPRN
1
EN
22
3
23
1
ACSET ACPRN
3
1
ACOFF
10K_0402_1%
2
1
PC31
1
2200P_0402_25V7K
PC33
2
PR54
100K_0402_1%
24
1
31
1
ACOFF
PR60
0.01U_0402_25V7K
2
31,35
6800P_0402_25V7K
2
2
IREF
1
31
PC36
1
2
PC44
0.01U_0402_25V7K
2
1
3
PACIN
4
S
PR64
47K_0402_5%
1
2
PQ18B
DMN66D0LDW-7_SOT363-6
5
G
PC35
1
2
0.1U_0603_25V7K
2
1
2
DCIN
1
D
PC25
2
2
2
1
1
VDD
S
2
PQ15
DTC115EUA_SC70-3
3
2
1
1
2
2
PR55
150K_0402_1%
PQ18A
DMN66D0LDW -7_SOT363-6
VIN
PR52
10K_0402_1%
@
PR51
14.3K_0402_1%
PU5
1
PR49
47K_0402_1%
1
2
ACSETIN
2
6
D
2
G
FSTCHG
1
3
31
PR50
10_1206_5%
2
PQ13
DTC115EUA_SC70-3
PR56
100K_0402_1%
2
PR53
10K_0402_1%
2
1
2
ACSETIN
BATT_ON
PR47
191K_0402_1%
PC77
1000P_0402_25V8J
2
1
PD8
2
1
6251VDD
2
PR46
200K_0402_1%
1
CSIP
PreCHG
4.7U_0805_25V6-K
2
1
CSIN
VIN
8
7
6
5
1
PC24
2
1
2
3
CHG_B+
0.1U_0402_25V6K
2
1
3
RB751V-40_SOD323-2
2
1
1
2
4
2
PC28
5600P_0402_25V7K
1
2
2
PR48
200K_0402_1%
1
PC29
2.2U_0603_6.3V6K
1
1
1
PQ10
DTA144EUA_SC70-3
PC27
0.1U_0603_25V7K
3
1
0.02_1206_1%
8
7
6
5
PL19
HCB4532KF-800T90_1812
PC23
1
2
3
PQ6
AO4435_SO8
4
1
2
3
4
8
7
6
5
2
VIN
B+
PR45
P3
PQ8
AO4407A_SO8
D
B+
PC75
10U_1206_25V6M
2
1
P2
PQ7
AO4435_SO8
C
PC74
10U_1206_25V6M
2
1
B
PC73
10U_1206_25V6M
2
1
A
@
G5209S31U_SSOP24
PR72
15.4K_0402_1%
1
2
1
31 CHGVADJ
PR73
31.6K_0402_1%
3
VIN
2
3
Iada=0~3.42A(65W)
CP= 92%*Iada; CP=3.147A
Vaclim=1.08V(65W)
PR68=75k
1
CP mode
@PR74
309K_0402_1%
PR45=0.02
6251VDD
2
@ PR75
10K_0402_1%
1
2
4.2V
1.882V
4.35V
3.2935V
PR252
47K_0402_1%
ACIN
18,31
@ PR76
47K_0402_1%
@ PC46
.1U_0402_16V7K
PACIN
1
2
PR250
10K_0402_1%
1
VCHLIM need over 95mV
0V
2
4V
ADP_V 31
1
IREF=0.254V~3.048V
PR251
10K_0402_1%
1
2
2
CHGVADJ
2
Vcell
1
CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge
1
CC=0.25A~3A
Vin Detector
1
ACPRN
2
PR249
14.3K_0402_1%
High 18.089V
Low 17.44V
4
3
2
PQ214
DTC115EUA_SC70-3
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
CHARGER
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
D
Sheet
37
of
45
5
4
3
2
1
PC47
1U_0603_10V6K
2VREF_51125
LG_5V
PR105
200K_0402_1%
2
EC_ON
S
2
1
2
3
2
1
PC58
4.7U_0805_10V6K
1
2
1
3
Compal Electronics, Inc.
Compal Secret Data
2009/01/23
Issued Date
1
PQ31
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DTC115EUA_SC70-3
5
A
Security Classification
3
31,33
D
2
G
PC60
2.2U_0603_10V6K
2
2
1
3
ACPRN
1
37
B
Ipeak=5A
Imax=3.5A
F=245kHZ
Total capacitor
220u
ESR=15m ohm
2
1
2
PR91
100K_0402_1%
A
2
PQ27
DTC115EUA_SC70-3
2
1
PR92
42.2K_0402_1%
1
+
@ PC56
680P_0603_50V8J
EN
1
VS_ON
1
1
PR90
100K_0402_1%
PQ32
2N7002W-T/R7_SOT323-3
VS
4
S
1
2
VL
4
1
DMN66D0LDW -7_SOT363-6
S
AO4712L_SO8
VL
2VREF_51125
PQ25B
5
G
PQ24
S IC UP6182CQAG VQFN 24P PW M
+5VALWP
PC54
220U_6.3V_M
19
1
LGATE1
PL5
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
@ PR86
4.7_1206_5%
LGATE2
2
PC59
0.1U_0603_25V7K
2
5
6
7
8
2
12
13
D
G
1
2
LX_5V
B++
3
6
D
PQ25A
DMN66D0LDW -7_SOT363-6
ENTRIP1
20
2
PR88
100K_0402_5%
2
1
ENTRIP2
PC57
1U_0402_6.3V6K
B
ENTRIP1
3
PHASE1
PR87
499K_0402_1%
1
2
B+
FB1
PHASE2
5
6
7
8
8
7
6
5
4
REF
21
11
NC
LG_3V
4
22
UGATE1
AO4712L_SO8
C
4
18
LX_3V
FB2
BOOT1
UGATE2
VREG5
10
TONSEL
BOOT2
PC52
PR84
.1U_0402_16V7K
BST_5V 1
2BST_5V1
1
2
0_0603_5%
UG_5V
VIN
9
UG_3V
5
23
17
BST_3V
18,36
PGOOD
16
VREG3
POK
24
GND
8
PQ22
AO4466L_SO8
VO1
SKIPSEL
VO2
15
1
2
3
PR83
2 1
2
BST_3V1
0_0603_5%
PC51
.1U_0402_16V7K
1
2
3
2
@ PR85
4.7_1206_5%
2
1
+
P PAD
7
PQ23
@ PC55
680P_0603_50V8J
2
1
1
PC53
220U_6.3V_M
+3VALWP
ENTRIP2
1
25
1
PL4
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
6
PU6
4
36
PR82
150K_0402_1%
2
1
1
3
2
1
PR81
150K_0402_1%
1
2
B++
PC49
10U_1206_25V6M
PR80
19.1K_0402_1%
1
2
14
PQ21
AO4466L_SO8
Ipeak=5A
Imax=3.5A
F=305kHZ
Total capacitor
220u
ESR=15m ohm
1
PR79
20K_0402_1%
1
2
2
PC50
4.7U_0805_10V6K
8
7
6
5
1
2
PC48
10U_1206_25V6M
1
PC61
10U_1206_25V6M
PC121
2200P_0402_50V7K
2
1
C
PR78
30K_0402_1%
1
2
ENTRIP1
+3VLP
1
2
2
B+
PR77
13K_0402_1%
1
2
ENTRIP2
B++
PL20
HCB4532KF-800T90_1812
D
2
D
4
3
2
Title
3VALWP/5VALWP
Size
Document Number
Rev
PWWAA LA6842P M/B
Date:
Wednesday, July 28, 2010
Sheet
1
38
of
0.2
45
C
D
5
VTTPW ROK_CPU
3
2
1
DL_1.05VS_VCCP
G5603RU1U_TQFN14_3P5X3P5
PR812
2.43K_0402_1%
2
1
PR808
4.02K_0402_1%
1
2
2
1
PR811
3.4K_0402_1%
1
2
@
1
2
PC122
2200P_0402_50V7K
2
1
PC802
4.7U_0805_25V6-K
2
1
PC62
10U_1206_25V6M
1
PR806
0_0402_5%
4
PC806
4.7U_0805_10V6K
9
2
2
1
1
PC808
DL
13.7K_0402_1%
1
10
+VTTP
@ PR804
4.7_1206_5%
2
VDD
1
B+
+5VALW
1
LX_1.05VS_VCCP
PR805
1
2
5
ILIM
11
680P_0603_50V7K
VTTPW ROK
14
15
TP
7
5,34
12
2
PC809
4.7U_0603_6.3V6K
1
PGOOD
LX
2
6
VFB=0.75V
DH_1.05VS_VCCP
PL802
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
3
2
1
FB
13
PQ802
VCC
5
DH
PC805
0.1U_0603_25V7K
BST_1.05VS_VCCP1
1
2
SI7170DP-T1-GE3_POWERPAK8-5
OUT
4
PR803
0_0603_5%
BST_1.05VS_VCCP
1
2
BST
3
EN_SKIP
TON
PGND
PR807
100_0603_1%
1
2
2
AGND
2
+5VALW
PU800
1
2
@ PC804
.1U_0402_16V7K
8
VTTP_EN
PC801
4.7U_0805_25V6-K
2
1
4
PR802
0_0402_5%
1
2
1
31
PC803
PR801
255K_0402_1%
1
2
PL801
HCB2012KF-121T50_0805
1
2
1.05VS_51117_B+
4.7U_0805_25V6-K
2
1
PQ801
1
5
B
TPCA8030-H_SOP-ADV8-5
A
+
PC807
390U_2.5V_M
2
2
+5VS
PR814
4.53K_0402_1%
PR809
10_0402_5%
2
1
1
VTT_SENSE
8
2
PR810
10K_0402_1%
PR813
10_0402_5%
2
1
3
3
8
VSS_SENSE_VTT
PJ20
+VTTP
2
2
1
1
+1.05VS
@ JUMP_43X79
(7.0A,280mils ,Via NO.=14)
4
4
Compal Secret Data
Security Classification
Issued Date
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
Compal Electronics, Inc.
+VTTP
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
Sheet
W ednesday, July 28, 2010
D
39
of
45
5
4
3
2
1
PL21
HCB2012KF-121T50_0805
D
2
ILIM
FB
VDD
10
PR132
18K_0402_1%
6
PGOOD
9
DL_1.5V
1
+5VALW
PQ35
+1.5VP
1
1
+
2
4
PC98
4.7U_0805_10V6K
3
2
1
1
2
G5603RU1U_TQFN14_3P5X3P5
AO4712L_SO8
PC95
220U_6.3V_M
1
@ PR130
4.7_1206_5%
VCC
5
DL
3
2
1
LX_1.5V
11
2
12
DH_1.5V
1
LX
PL10
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
2
13
PC94
0.1U_0603_25V7K
1
2
@ PC97
680P_0603_50V8J
DH
AO4466L_SO8
5
6
7
8
14
15
1
TP
BST
OUT
2BST_1.5V1
PR129
0_0603_5%
4
7
C
3
PGND
2
PC96
4.7U_0603_6.3V6K
TON
EN_SKIP
PR131
100_0603_1%
1
2
2
AGND
2
PU10
1
+5VALW
@PC93
@
PC93
.1U_0402_16V7K
B+
4
BST_1.5V 1
8
SYSON
PR128
0_0402_5%
1
2
1
31
PR127
255K_0402_1%
1
2
2
PQ34
1
PC123
2200P_0402_50V7K
2
5
6
7
8
D
2
PC92
4.7U_0805_25V6-K
1
PC91
4.7U_0805_25V6-K
2
1
1.5V_B+
Ipeak=9A
Imax=6.3A
F=313kHZ
Total capacitor
610u
ESR=5m ohm
C
PR134
10K_0402_1%
2
1
PR133
10K_0402_1%
1
2
B
B
A
A
Compal Secret Data
Security Classification
Issued Date
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
+1.5VP
Size
Document Number
Custom
Date:
Rev
0.2
PWWAA LA6842P M/B
Wednesday, July 28, 2010
Sheet
1
40
of
45
A
B
C
D
1
1
+1.5V
PJ23
@ JUMP_43X79
1
2
2
1
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
+5VALW
1
6
NC
2
VCNTL
GND
PC99
1U_0603_10V6K
1
+0.75VSP
2
1
2
1K_0402_1%
1K_0402_1%
1
PR135
2
1
PR138
S
VIN
2
UP7711U8_PSOP8
PC102
0.1U_0402_10V7K
2
@ PC101
.1U_0402_16V7K
D
2
G
1
34 0.75VR_EN#
2
2
PR137
0_0402_5%
1
2
PQ36
SSM3K7002FU_SC70-3
1
9,34 SUSP
1
@ PR136
0_0402_5%
1
2
3
4.7U_0805_6.3V6K
PC100
PU11
1
PC103
10U_0805_6.3V6M
2
2
2
1
2
PC182
PC181
1U_0603_10V6K
1
1
2
2
PJ181
@ JUMP_43X39
+5VALW
1
+3VALW
3
3
4.7U_0805_25V6-K
PU180
1
2
APL5930KAI-TRG_SO8
2
PR182
3K_0402_1%
1
2
2
FB
+1.8VSP
2
PR184
2.4K_0402_1%
PC184
22U_0805_6.3V6M
2
@ PC187
0.47U_0402_6.3V6K
3
4
PC183
0.01U_0402_25V7K
EN
POK
VOUT
VOUT
1
8
7
1
VCNTL
VIN
VIN
1
PR181
0_0402_5%
1
2
GND
SUSP#
1
27,31,34
6
5
9
4
4
Compal Secret Data
Security Classification
Issued Date
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
Compal Electronics, Inc.
0.75VSP/+1.8VSP
Size
Document Number
PWWAA LA6842P M/B
Date:
Sheet
W ednesday, July 28, 2010
D
41
of
45
Rev
0.2
2
1
CPU_VID4
2
1@ PR151 1K_0402_1%
CPU_VID4
2
1
CPU_VID5
2
1 PR154 1K_0402_1%
CPU_VID5
2
1 @ PR155 1K_0402_1%
CPU_VID6
2
1@ PR157 1K_0402_1%
CPU_VID6
2
1
H_DPRSLPVR
2
1 PR160 1K_0402_1%
H_DPRSLPVR
2
1 @ PR161 1K_0402_1%
H_PSI#
2
1
PR152 1K_0402_1%
PR158 1K_0402_1%
PR163 1K_0402_1%
4
+VTT
1
2
1
2
PC117
0.22U_0603_25V7K
1
2
PHASE2
@ PR178 1K_0402_1%
1
2
+VTT
PR179
1
8
H_PSI#
PR180
1
2
147K_0402_1%
40
39
38
37
36
35
34
33
32
31
PC130
2
1
PR169
4.7_1206_5%
2
0_0402_5%
2
8
D
2 1
3
2
1
PC143
0.22U_0603_25V7K
1
2
3
2
1
VSUM-
@ PR220
100_0402_1%
1
Layout Note:
Place near Phase1 Choke
2
PC142
4.7U_0805_25V6-K
2
1
1
2
PC140
4.7U_0805_25V6-K
2
PR212
10K_0402_5%
2009/01/23
Issued Date
VSUM+
V2N
B
ISEN1
Deciphered Date
Title
+CPU_CORE
Size
C
Date:
5
4
3
A
Compal Electronics, Inc.
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6
2
VSUM-
Compal Secret Data
Security Classification
7
2
PR213
1_0402_5%
@ PR216
0_0402_5%
1
A
8
+CPU_CORE
V1N
1
1
3
1
PR211
3.65K_0805_1%
2
1
1
PR210
4.7_1206_5%
2
4
4
1
LGATE1
2
PH4
10K_0402_1%_ERTJ0EG103FA
2
PC139
470P_0603_50V8J
2
1
0.36UH_FDU1040J-H-R36M=P3_33A_20%
PHASE1
5
2
C
PL14
PC150
680P_0603_50V8J
1
@ PC186
1200P_0402_50V7K
1
PR215
11K_0402_1%
2
1
2
PR214
1.2K_0402_1%
4
PR207 2.2_0603_1%
1
2 BOOT1_1
PQ43
TPCA8030-H_SOP-ADV8-5
UGATE1
PR208
2.61K_0402_1%
2
1
PC145
0.22U_0603_10V7K
2
1
@ PC147
0.01U_0402_25V7K
1
5
1
1
2
VSSSENSE
PC151
.1U_0402_16V7K
2
1
2
1
@ PR219 10_0402_5%
1
2
PC149
330P_0402_50V7K
1
2
0_0402_5%
2
2
PC148
1000P_0402_50V7K
PR217
1
@ PR206
82.5_0402_1%
1
2
PC146
330P_0402_50V7K
2
2
VSUM2
0_0402_5%
PR204
8.87K_0402_1%
+CPU_B+
VSUM+
@ PR205 10_0402_5%
1
Arrandale -- 2 phase 1H1L
IMVP_IMON
PC135
0.22U_0603_25V7K
1_0402_5%
2
+5VALW
PC144
0.047U_0402_16V7K
2
1
2
PR209
B
PR201
PC134
0.22U_0603_25V7K
1
2
1
0_0402_5%
PC133
1U_0603_10V6K
2
1
2
0_0402_5%
1
2
PR203
1
VSSSENSE
F
1
PR195
1
0_0402_5%
2
+CPU_B+
BOOT1
ISEN1
VCCSENSE
ISEN2
0_0402_5%
2
PR198
1
1
ISEN2
Layout Note:
PH3 place near
Phase1 L-MOS
8
PR186
1
1
PR199
412K_0402_1%
PR202
8
VSUM-
E
2
C
V1N
2
2
11
12
13
14
15
16
17
18
19
20
AGND
1
1
+CPU_CORE
PR171
1_0402_5%
@ PR175
0_0402_5%
1
PR183
0_0402_5%
30
29
28
27
26
25
24
23
22
21
PC128
1U_0603_10V6K
2
1
41
PC138 0.22U_0402_6.3V6K
PC132
150P_0402_50V8J
PR194
562_0402_1%
2
1
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
PR196
2.43K_0402_1%
1
2
2
PC131
10P_0402_50V8J
2
2
390P_0402_50V7K
1
1
2
PC126
22P_0402_50V8J
PC137 0.22U_0402_6.3V6K
2
1
PR188
8.06K_0402_1%
1
2
PC127
1000P_0402_50V7K
2
1
PR189
249K_0402_1%
1
2
1
D
G
+CPU_CORE
V2N
+5VALW
PC119
1U_0603_10V6K
1
2
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
2
3
4
5
6
7
8
9
10
E
1
2
H
ISL62883CHRZ-T_QFN40_5X5~D
PU13
@
1
0_0402_5%
2
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
F
2
+
B+
VSUM+
2
3
2
1
2
PQ44
SI7170DP-T1-GE3_POWERPAK8-5
VGATE
PR174
1.91K_0402_1%
1
18,31
PR177
0_0402_5%
1
4
PC118
680P_0603_50V8J
LGATE2
PQ38
SI7170DP-T1-GE3_POWERPAK8-5
CLK_ENABLE#
2
2
PR172
1.91K_0402_1%
1
+
1
1
3
5
13 CLK_ENABLE#
+3VS
2
4
2
1
PR170
3.65K_0805_1%
2
1
8 H_DPRSLPVR
+
1
PL12
0.36UH_FDU1040J-H-R36M=P3_33A_20%
UGATE2
PR168 0_0402_5%
G
1
1
VR_ON
PR166 2.2_0603_1%
BOOT2_2
1
2
BOOT2
PR167 0_0402_5%
31
PR149 1K_0402_1%
@ PC115
0.1U_0603_25V7K
2
1
CPU_VID3
2
1@ PR148 1K_0402_1%
PC185
68U_25V_M_R0.36
2
PC111
68U_25V_M_R0.36
CPU_VID3
PL11
HCB4532KF-800T90_1812
1
2
PC114
68U_25V_M_R0.36
1 @ PR147 1K_0402_1%
1
1 @ PR145 1K_0402_1%
2
2
2
CPU_VID2
1
PC113
4.7U_0805_25V6-K
2
1
CPU_VID1
1 PR146 1K_0402_1%
PR173
10K_0402_5%
CPU_VID6
1 PR144 1K_0402_1%
2
PC141
4.7U_0805_25V6-K
2
1
CPU_VID5
8
2
CPU_VID2
2
+CPU_B+
2
8
CPU_VID1
3
1
CPU_VID4
1 @ PR143 1K_0402_1%
2
CPU_VID3
8
2
PC116
4.7U_0805_25V6-K
CPU_VID2
8
CPU_VID0
PC120
4.7U_0805_25V6-K
8
1 PR142 1K_0402_1%
PC110
2200P_0402_50V7K
2
1
CPU_VID1
4
2
PC112
470P_0603_50V8J
2
1
CPU_VID0
8
5
CPU_VID0
PQ37
TPCA8030-H_SOP-ADV8-5
8
6
3
2
1
H
7
5
8
2
Document Number
PWWAA LA6842P M/B
Wednesday, July 28, 2010
Sheet
42
1
of
45
Rev
0.2
A
B
C
D
E
F
G
H
2
1
17
4
3
2
1
33
1
2
1
2
PC153
4.7U_0805_25V6-K
PQ46
TPCA8030-H_SOP-ADV8-5
PC152
4.7U_0805_25V6-K
1
2
2
PC159
2.2U_0603_10V6K
2
1
+GFX_COREP
Ipeak=22A
Imax=15.4A
F=350kHZ
Total capacitor
720u
ESR=3.75m ohm
1
@ PR235
4.7_1206_5%
+
PC161
390U_2.5V_M
2
@ PC163
680P_0603_50V8J
PH5
220K_0402_5%_ERTJ0EV224J~D
2
Place RTH1 close to inductor
on the same layer
PR242
71.5K_0402_1%
2
1
1
1
1
PC165
560P_0402_50V7K
PR246
165K_0402_1%
2
2
PC164
1000P_0402_50V7K
1
3
1
1
PR247
40.2K_0603_1%
2
PC166
1000P_0402_50V7K
B+
12
GFX_DRVL
18
2
Connect to input caps
1
PL16
0.36UH_PCMC104T-R36MN1R105_30A_20%
1
2
2
19
+5VALW
PQ47
SI7170DP-T1-GE3_POWERPAK8-5
3
2
1
20
5
26
2
GFX_SW
1
2
2
5
1
CSCOMP
CSFB
GFX_DRVH
21
4
16
15
22
PR234
PC157
0_0603_5%
0.22U_0603_25V7K
2GFX_BOOST-1
1
2
PC168
4.7U_0805_25V6-K
1
GFX_VCC
VID6
VID5
27
VID4
VID3
29
28
LLINE
CSREF
14
RT
AGND
23 GFX_BOOST 1
GFX_RAMP-1
2
9
9
VCC_AXG_SENSE
VSS_AXG_SENSE
+GFX_B+
13
12
GFX_RAMP
IREF
9
PR240
237K_0402_1%
1
2 GFX_RPM
GFX_CSCOMP 1
PR239
80.6K_0402_1%
GFX_IREF
1
2
2
2
1
1
3
AGND
24
GFX_CSCOMP
PR244
0_0402_5%
PR248
1K_0402_1%
2
1
GFX_CSFB
PR243
0_0402_5%
GFX_CSCOMP
Avoid high dV/dt
RAMP
ILIM
PC154
1U_0805_25V6K
1
1
2
2
PR237
20K_0402_1%
PR238
10.7K_0402_1%
DRVL
PGND
2
PC162
470P_0402_50V8J
PU15
GPU
GFX_ILIM 8
PR236
1K_0402_1%
PVCC
COMP
GFX_VCC 7
PR245
422K_0402_1%
1
FB
GFX_COMP 6
11
2
2GFX_COMP-1
1
5
ADP3211AMNR2G_QFN32_5X5
GFX_RT
1
PC160
47P_0402_50V8J
VID2
SW
FBRTN
RPM
GFX_FB
2
VID1
DRVH
CLKEN#
4
1
30
BST
IMON
3
PC158
220P_0402_50V7K
31
32
EN
PWRGD
2
10
PC156
1000P_0402_50V7K
VID0
1
2
1
VSS_AXG_SENSE
2
2
9
9
9
PR231
PR226
PR227
1
1
2
VCC
1
GFXVR_IMON
PR241
340K_0402_1%
1
2
1
PR233
10K_0402_1%
PL15
HCB4532KF-800T90_1812
PR228
10_0603_1%
25
PR225
1
PR223
PR224
1
1
1
+GFX_B+
+3VS
PR232
6.98K_0402_1%
2
1
2
GFXVR_VID_2
9
GFXVR_VID_3
9
GFXVR_VID_4
9
GFXVR_VID_5
9
GFXVR_VID_6
9
GFXVR_EN
GFXVR_IMON
PC155
0.056U_0402_16V7K
PR222
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
GFXVR_IMON
+5VALW
GFX_EN
1
@ PR229
300K_0402_5%
1
1
PR221
+1.05VS
9
GFXVR_VID_1
1
GFXVR_VID_0
1
PC167
1000P_0402_50V7K
Switchable -- mount
Non Swithchable--non mount @
Shortest the
net trace
4
4
2009/10/02
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2010/10/02
Title
+GFX_COREP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
PWWAA LA6842P M/B
Date:
A
B
C
D
E
F
Document Number
G
Wednesday, July 28, 2010
Sheet
43
H
of
45
Rev
0.2
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------42
BOM modify
2010/07/13
2010/07/13
2010/07/23
2010/07/26
2010/07/26
2010/07/26
2010/07/26
2010/07/26
43
36
36
37
38
39
40
Change PL12,PL14 to SH00000IN00
Change PL16 to SH00000IN00
Change PC19 to SE070104Z80
Add PD6,PD7
Add
Add
Add
Add
BOM modify
BOM modify
EMI request
EMI request
EMI request
EMI request
EMI request
PC73,PC74,PC75(10U_1206)
PC121(2200P_0402),PC61(10U_1206)
PC122(2200P_0402),PC62(10U_1206)
PC123(2200P_0402)
Compal Secret Data
Security Classification
Issued Date
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Compal Electronics, Inc.
Power PIR
Size
Document Number
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
44
of
45
5
4
3
2
1
PIR (Product Improve Record)
PWWAA LA-6842P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2010/07/31
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------D
1. 20100714 / Page13 --> add 10u Cap to +1.5VS_CK505
For eSATA transmit issue
---> not add 10u Cap into schematic yet
D
C
C
B
B
A
NWQAA LA-6061P SCHEMATIC CHANGE LIST
REVISION CHANGE: 1.0 TO 2.0
GERBER-OUT DATE: 2010/03/19
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
3/17
29
Change cardreader to JMB385/389
For customer request
2
3/18
31
Remove D86
For ESD request
3
3/18
22
Add R52
For CRT wave issue
4
3/19
22
Change L12 to 2.2 ohm
For CRT wave issue
5
3/22
15
Add D54
For HDMI CEC issue
6
3/24
13
Change C213 to 1U
For NALAA ESATA performance low issue
---------------------------------------------------------------------------------------------------------------------
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/21
Issued Date
Deciphered Date
2011/06/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
HW-PIR
Size
Document Number
Custom
Rev
0.2
PWWAA LA6842P M/B
Date:
W ednesday, July 28, 2010
Sheet
1
45
of
45