L4: Sequential Building Blocks
(Flip-flops, Latches and Registers)
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with permission.
Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in
Electrical Engineering and Computer Science at the University of California, Berkeley)
and Prof. Gaetano Borriello (University of Washington Department of Computer
Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design.
2nd ed. Prentice-Hall/Pearson Education, 2005.
J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.
Prentice Hall/Pearson, 2003.
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Introductory Digital Systems Laboratory
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Combinational Logic Review
in0
in0
in1
in1
Combinational
Circuit
inM-1
inN-1
ƒ Combinational logic circuits are memoryless
ƒ No feedback in combinational logic circuits
ƒ Output assumes the function implemented by the
logic network, assuming that the switching
transients have settled
ƒ Outputs can have multiple logical transitions
before settling to the correct value
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A Sequential System
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Registers
Q
D
Memory element
CLK
ƒ Sequential circuits have memory (i.e., remember the past)
ƒ The current state is “held” in memory and the next state is
computed based the current state and the current inputs
ƒ In a synchronous systems, the clock signal orchestrates the
sequence of events
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A Simple Example
Adding N inputs (N-1 Adders)
in0
in1
in2
inN-1
Using a sequential (serial) approach
reset
in
DQ
Current_Sum
clk
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Implementing State: Bi-stability
Vi2 = Vo1
Vo1 = Vi2
Vo2 = Vi1
Point C is
Metastable
C
Vi2
V o1
V i1
V o2
V i2 = V o
1
δ
Vi1 = V o2
A
Points A and
B are stable
(represent 0 & 1)
A
V i 2 = V o1
C
B
B
V i 1 = V o2
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δ
Introductory Digital Systems Laboratory
V i1 = V o2
5
NOR-based Set-Reset (SR) Flipflop
SR = 00, 10
SR = 00, 01
S
Q
R
Q
S
SR = 1 0
Q
Q
R
Reset
S
R
Q
Q
0
0
Q
Q
1
0
1
0
0
1
1
1
0
0
1
0
QQ
01
QQ
10
SR = 0 1
SR = 0 1
SR = 1 0
SR = 11
SR = 1 1
SR = 1 1
QQ
00
Forbidden State
Hold
Set
SR = 0 0
SR = 0 0
Reset
Set
R
S
Q
??
Q
ƒ Flip-flop refers to a bi-stable element (edge-triggered registers are also
called flip-flops) – this circuit is not clocked and outputs change
“asynchronously” with the inputs
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Making a Clocked Memory Element:
Positive D-Latch
D
Q
S
CLK
R
hold
D
Q
sample
hold
sample
hold
R and S
G
clock
clk
ƒ A Positive D-Latch: Passes input D to output Q when CLK is
high and holds state when clock is low (i.e., ignores input D)
ƒ A Latch is level-sensitive: invert clock for a negative latch
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Multiplexor Based Positive & Negative Latch
2:1 multiplexor
in0
Positive Latch
Negative Latch
0
1
0
out
in1
1
D
Q
1
D
Q
0
SEL
Out = sel * in1 + sel * in0
CLK
CLK
clk
clk
"data"
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"remember"
"load"
"stored value"
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74HC75 (Positive Latch)
2
1D
13
LE1-2
D
Q
1Q
16
1Q
1
2Q
15
CP
Q
L1
3
2D
D
Q
CP
Q
2Q
14
Inputs
Operating Modes
LEn-n
Outputs
nD
nQ
nQ
L2
6
3D
4
LE3-4
D
Q
3Q
10
Data Enabled
3Q
11
Data Latched
4Q
9
4Q
8
CP
Q
H
L
L
H
H
H
H
L
L
X
q
q
L3
7
4D
D
Q
CP
Q
Figures by MIT OpenCourseWare.
L4
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Building an Edge-Triggered Register
Negative latch
D
D Q
Positive latch
QM
G
D
Q
D Q
D Q
Q
G
CLK
CLK
Slave
Master
CLK
0
1
D
0
QM
QM
Q
Master-Slave Register
†
†
„
D
CLK
CLK
„
1
Q
Image by MIT OpenCourseWare.
Use negative clock phase to latch inputs into first latch
Use positive clock to change outputs with second latch
View pair as one basic unit
†
master-slave flip-flop twice as much logic
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Latches vs. Edge-Triggered Register
Edge triggered device sample inputs on the event edge
7474
D
Q
Transparent latches sample inputs as long as the clock is
asserted
Timing Diagram:
Clk
Positive edge-triggered
register
D
7475
D
Clk
Q
C
Clk
Level-sensitive
latch
Bubble here
for negative
edge triggered
register
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Q
7474
Q 7475
Behavior the same unless input changes
while the clock is high
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Important Timing Parameters
Clock:
Periodic Event, causes state of memory
element to change
Clock
Tsu
Th
memory element can be updated on the:
rising edge, falling edge, high level, low level
Input
There
Thereis
isaatiming
timing
"window"
"window"around
aroundthe
the
clocking
clockingevent
event
during
duringwhich
whichthe
the
input
inputmust
mustremain
remain
stable
stable and
and
unchanged
unchangedin
inorder
order
to
tobe
berecognized
recognized
Setup Time (Tsu)
Minimum time before the clocking event by
which the input must be stable
Hold Time (Th)
Minimum time after the clocking event during
which the input must remain stable
Propagation Delay (Tcq for an edge-triggered
register and Tdq for a latch)
Delay overhead of the memory element
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The J-K Flip-Flop
J
K
S
R
Q
Q
100
J
J
K
Q+
Q+
0
0
Q
Q
0
1
0
1
1
0
1
0
1
1
Q
Q
K
Q
\Q
„
Eliminate the forbidden state of the SR Flip-flop
„
Use output feedback to guarantee that R and S are
never both one
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J-K Master-Slave Register
Sample inputs while clock low
Sample inputs while clock high
J
S
Q
R
K
CLK
Q
Set
P
P
Reset
1's
Catch
Toggle
J
S
Q
R
Q
100
Correct Toggle
Operation
K
Clk
J
φ
K
Q
P
Master
outputs
\P
Q
Q
Slave
outputs
\Q
Is there a problem with this circuit?
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Pulse Based Edge-Triggered J-K Register
φ
Input
X
Input
φ
Output
X
tpLH
Schematic
Output
J
φ
S
Q
R
Q
K
J
Q
φ
K
Q
JK Register Logic Symbol
JK Register Schematic
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Pulse-Triggered Registers
Ways to design an edge-triggered sequential cell:
Master-Slave Latches
L1
Data
Pulse-Based Register
L2
D Q
D Q
Clk
Clk
Latch
Data
Clk
D Q
Clk
Clk
Short pulse around clock edge
ƒ Pulse registers are widely used in high-performance
microprocessor chips (Sun Microsystems, AMD, Intel, etc.)
ƒ The can have a negative setup time!
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D Flip-Flop vs. Toggle Flip-Flop
1
D Q
D Flip-Flop
0
Clk
D
QN
0
0
1
1
0
1
1
1
0
0
1
T Q
T (Toggle)
Flip-Flop
0
Clk
T
QN
0
Q N-1
1
QN-1
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1
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Realizing Different Types of Memory
Elements
Characteristic Equations
D:
Q+ = D
J-K:
Q+ = J Q + K Q
T:
Q+ = T Q + T Q
E.g., J=K=0, then Q+ = Q
J=1, K=0, then Q+ = 1
J=0, K=1, then Q+ = 0
J=1, K=1, then Q+ = Q
Implementing One FF in Terms of Another
D
J Q
C
K Q
Q
K
D Q
J
D implemented with J-K
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C Q
J-K implemented with D
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Design Procedure
Excitation Tables: What are the necessary inputs to cause a particular kind of
change in state?
Q Q+
0 0
0 1
1 0
1 1
T
0
1
1
0
J K
0 X
1 X
X 1
X 0
D
0
1
0
1
D
Implementing D FF with a J-K FF:
Q
0
1
1) Start with K-map of Q+ = ƒ(D, Q)
0
0
1
2) Create K-maps for J and K with same inputs (D, Q)
1
0
1
3) Fill in K-maps with appropriate values for J and K
to cause the same state changes as in the original K-map
D
0
1
0
0
1
1
X
X
Q
E.g., D = Q= 0, Q+ = 0
then J = 0, K = X
J= D
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D
0
1
0
X
X
1
1
0
Q
Q+ = D
K =D
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Design Procedure (cont.)
Implementing J-K FF with a D FF:
1) K-Map of Q+ = F(J, K, Q)
2,3) Revised K-map using D's excitation table
its the same! that is why design procedure with D FF is simple!
J
JK
Q
0
1
00
01
11
10
0
0
1
1
1
0
0
1
K
Q+ = D = JQ + KQ
Resulting equation is the combinational logic input to D
to cause same behavior as J-K FF. Of course it is identical
to the characteristic equation for a J-K FF.
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System Timing Parameters
In
D Q
Combinational
Logic
Clk
Clk
Register Timing Parameters
Tcq : worst case rising edge
clock to q delay
Tcq, cd: contamination or
minimum delay from
clock to q
Tsu: setup time
Th: hold time
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D Q
Logic Timing Parameters
Tlogic : worst case delay
through the combinational
logic network
Tlogic,cd: contamination or
minimum delay
through logic network
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System Timing (I): Minimum Period
CLout
In
Combinational
Logic
D Q
D Q
Clk
Clk
CLK
Th
Th
IN
Tsu
Tsu
Tcq
Tcq
FF1
Tcq,cd
Tlogic
Tcq,cd
CLout
Tl,cd
Tsu2
T > Tcq + Tlogic + Tsu
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System Timing (II): Minimum Delay
CLout
In
Combinational
Logic
D Q
D Q
Clk
Clk
CLK
Th
Th
IN
Tsu
FF1
Tcq,cd
CLout
Tl,cd
Tcq,cd + Tlogic,cd > Thold
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Shift-Register
Typical parameters for Positive edge-triggered D Register
„
D
Tsu Th
20ns 5ns
CLK
Th
5ns
all measurements are made
from the clocking event that is,
the rising edge of the clock
Tw 25ns
Tplh
25ns
13ns
Q
„
Tsu
20ns
Tphl
40ns
25ns
Shift-register
IN
DQ
Q0
DQ
Q1
100
OUT
IN
Q0
Q1
CLK
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CLK
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