Master-slave D flip-flop
• When clock=1, the master tracks the values of the D
input signal and the slave does not change
– Thus Qm follows any changes in D and Qs remains constant
• When the clock signal changes to 0, the master
stage stops following the changes in the D input
signal
• At the same time, the slave stage responds to the
value of Qm and changes states accordingly
• Since Qm does not change when clock=0, the slave
stage undergoes at most one change of state during
a clock cycle
• From an output point of view, the circuit changes Qs
(its output) at the negative edge of the clock signal
ECE380 Digital Logic
Flip-Flops, Registers and
Counters:
Flip-Flops
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-1
Flip-flops
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-4
Master-slave D flip-flop
• The gated latch circuits presented are level
sensitive and can change states more than
once during the ‘active’ period of the clock
signal
• Circuits (storage elements) that can change
their state no more than once during a clock
period are also useful
• Two types of circuits with such behavior
Clock
D
Qm
Q = Qs
Q
D
– Master-slave flip-flip
– Edge-triggered flip-flop
clock
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-2
Q
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-5
Master-slave D flip-flop
Edge-triggered flip-flop
• Consists of 2 gated D latches
• A circuit, similar in functionality to the master-slave
D flip-flop, can be constructed with 6 NAND gates
– The first, master, changes its state while clock=1
– The second, slave, changes its state while
clock=0
Master
D
Clock
D
Q
Clk Q
Q
Slave
m
D
Q
Clk Q
Qs
2
Q
Dr. D. J. Jackson Lecture 25-3
P3
P1
5
Q
6
Q
D
Q
Clock
3
Q
38 transistors
Electrical & Computer Engineering
1
D
4
Electrical & Computer Engineering
P2
P4
clock
Q
Positive-edge-triggered
D type flip-flop
24 transistors
Dr. D. J. Jackson Lecture 25-6
1
Edge-triggered flip-flop
T flip-flop
• The previous circuit responds on the positive
edge of the clock signal
• A negative-edge triggered D flip-flop can be
constructed by replacing the NAND with NOR
gates
• Another flip-flop type, the T flip-flop, can be
derived from the basic D flip-flop presented
• Feedback connections make the input signal D equal
to the value of Q or Q’ under control of a signal
labeled T
Q
D
D
Q
D
clock
clock
Q
Positive-edge-triggered
D type flip-flop
Q
Negative-edge-triggered
D type flip-flop
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-7
Comparing D storage elements
D
clock
D
clk Q
D
Qb
Q
D
Q
Qc
Q
Q
Q
Clock
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-10
T flip-flop
– This feature makes the T flip-flop a useful element
when constructing counter circuits
clock
Q
Q
• The name T derives from the behavior of the
circuit, which ‘toggles’ its state when T=1
Qa
Q
T
D
T Q(t+1)
Clock
Qa
0
Q(t)
Q
b
T
1
Q’(t)
Q
Q
c
T
Q
Q
clock
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-8
Electrical & Computer Engineering
Q
Positive edge triggered
Dr. D. J. Jackson Lecture 25-11
Clear and preset inputs
JK flip-flop
• It may be desirable to specifically set (Q=1)
or clear (Q=0) a flip-flop
• Practical flip-flops often have preset and
clear inputs
• The JK flip-flop can also be derived from
the basic D flip-flop such that
– Generally, these inputs are asynchronous (they
do not depend on the clock signal)
Preset’
D
clock
Q
As long as Preset’=0, Q=1
Q
As long as Clear’=0, Q=0
D=JQ’+K’Q
• The JK flip-flop combines aspects of the SR
and the T flip-flop
– It behaves as the SR flip-flop (where J=S and
K=R) for all values except J=K=1
– For J=K=1, it toggles like the T flip-flop
Clear’
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-9
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-12
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JK flip-flop
J
D Q
Q
Q
Q
K
Clock
J
K Q(t+1)
0
0
Q(t)
0
1
1
1
0
1
0
1
Q’(t)
Electrical & Computer Engineering
J
Q
clock
K
Q
Positive edge triggered
Dr. D. J. Jackson Lecture 25-13
JK flip-flop timing diagram
Complete the following timing diagram
Clk
K
J
Q
Q
1
0
1
0
1
0
1
0
1
0
Time
Electrical & Computer Engineering
Dr. D. J. Jackson Lecture 25-14
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