Factors which influence in many core processors
ABSTRACT: The applications for multicore and manycore
microprocessors as RISC-V are currently useful for the advantages
of their friendly nature, compared to previous chips, which have
caused a great demand for these multi-core or many-core
processors used in parallel computing for fluid emulation mainly on
the atmosphere of the earth, and other applications.
The result of this research, is the focus in determining the factors
that influence high-performance systems, after reviewing and
considering various authors, for its realization. This research focuses
on two factors which influence on the data in computer systems
shared memory (multi-core and many-core architecture) being
these topology and memory consistency.
Factors which influence the performance
Algorithms
Topology
System
operating
Architecture
Taxonomy
Programming
Model
Manycore
Heterogeneous
Languages
programming
Homogeneous
Technology
Memory
Model
Memory
Cache
Software-Defined Error-Correcting Codes
Errorsinmemoryoftenresultinsystem-levelcrashes.
Currenterror-correctiontechniquesarecostly andareoblivious
totheunderlyingdatastoredinmemory.
SDECCpushesbeyondcurrenterror-correctioncapabilitiesbycombining
threelayers:
• System-levelfaulttolerance
• Error-correctingcodes
• Side-informationaboutdataand
instructionsinmemory
à RISC-V!J
WASP-SC
AustinHarris,Rohith Prakash
TheUniversityofTexasatAustinSPARKLab
• Goal:defendagainstutilization side-channels
• E.g.sharedmemorycontrollers,hardwareaccelerators
• Normalization(e.g.partitioning,worst-case)infeasible
• Solution:shapevictim’sutilizationtobestatisticallyindistinguishable
acrossdifferentinputs
• Optimallyminimizesslowdownwithinprovablyconfigurableprivacybounds
• ModifyRockettohavecoressharingSHA3accelerator
• Sendcommandsthroughqueuewithourtrafficshapingdefense
V603 RV64GCP RISC-V MCU
P8
P6
16-256
KB
RAM
w/ ECC
P9
16KB
ROM
w/ ECC
P10
4KB
OTP
P5
P4
64b
RISC-V
CPU x 2
SIMD
Lockstep
256MHz
512MHz
P1
Crystal
Clock
P0
Power
Regulator
Asymmetric
RC
CPU
Crypto
Oscillator
Tight
for
Couple
CPU
InterTight
face
Couple
Interface
DMA
24CH
Platform Level Interrupt Controller
(PLIC)
P12
P13
P15
P2
Physical Memory Protection (PMP)
P11
P14
P3
Reset
Crystal
Oscillator
PLL
P16
P17
P18
CAN
With
FD
Extension
GPIO
External
Flash
Security
Logic
P19
P20
ADC
12bit
10MHz
SIP
= System in a Package
ICE
FPGA
ICE
Debugger
Quad
SPI
Interface
Peripheral Interconnect
SW I2C
Fast: 400kbps
Fast+:1Mbps
HS:3.4Mbps
ICE I/F
TDI
TDO
TCK
TMS
TRST_L
DBREQ_L
DBRDY
P7
SCLK
CS#
IO0
IO1
WP#
HOLD#
256KB /
128KB /
64KB
Flash
80-104MHz
Uniform
Sector
Serial Flash
VDDM
(1.8V / 3.3V)
PWM
Trace Info.
(e.g. Ether)
VSSM
VSSA = 0V
VDDA =1.1V 3.3V
VDD = 3.3V
VSS = 0V
Sub-microsecondAdaptiveVoltage
Scalingina28nmRISC-VSoC
Demo:Runninguser-modeprogramsinLinuxonRISC-V
silicontodemonstrateintegratedpowermanagement
Synchronizers
VOLTAGE AND CLOCK
GENERATION (0.4 mm2)
Back-Bias
Generator
To
scope
INTEGRATED
SRAM
BIST MEASUREMENT
Z-scale PMU
Programmable
current mirror load
8KB Scratchpad
CORE (1.07 mm )
...
Vector Accelerator
...
Branch Prediction
(16KB Vector RF uses eight
custom 8T SRAM macros)
Scalar
RF
int
Voltage
and Clock
Generation
Core
Clock
Pre-divide
SC-DCDC
Toggle Clock
Voltage
Setting
Programmable
counter
Programmable
counter
1GHz Reference
Power management algorithm
loaded into scratchpad memory
(compiled from C/C++)
Z-scale PMU
execute power management algorithm
...
FPU
int
int
int
int
Crossbar
Functional units
(64-bit Int. Mul., SP/DP FMA)
int
DC-DC controller
16KB Scalar
Inst. Cache
32KB Shared
Data Cache
8KB Vector
Inst. Cache
(Custom 8T
SRAM Macros)
(Custom 8T
SRAM Macros)
(Custom 8T
SRAM Macros)
Arbiter
core clk
Adaptive clock
generator
Async. FIFO/Level shifters
between domains
Rocket Processor
and Vector
Accelerator
Adaptive Clock
Generator
SC-DCDC Unit Cells
Vref
SC-DCDC Unit Cells
Vector Memory Unit
+
DCDC toggle
48 switched-capacitor
DC-DC unit cells
FSM
Vector Issue Unit
Rocket Core
Vout
Iref
Vout waveform
reconstruction
Iload
Set body bias
Set DC-DC Vout
2
1.8V
1.0V
1.0V
Toggle
Counter
Clock
Counter
NWELL PWELL
To
scope
POWER MANAGEMENT
(0.1 mm2)
Digital IO pads to wire-bonded chip-on-board UNCORE
To/from off-chip FPGA FSB and DRAM
Power Measurement
Counters
SC-DCDC Control
PMU
BenKeller•5th RISC-VWorkshop•November29,2016
RV128 The Path to Embedded Exascale
Courtesy Kogge et als 2008
UNNI: An open source core for easy transition
from ARM Cortex-M0 to RISC-V
• Von Neumann architecture with
2-stage pipeline
• Optimized for ASIC implementation
• Written in SystemVerilog
• Low latency interrupt handling with
tail-chaining and pre-emption
Mikael Korpi
OKiM Technologies
Full-Featured RISC-V Debug Solution
Tim Newsome <[email protected]>
• It works in silicon!
• Download directly to flash
• Implementations
Demo Setup:
• Open Source
32x16 LED Display
laptop
GPIO
gdb
SiFive board
OpenOCD
SiFive E300U Coreplex
RV32ACFIM
JTAG
USB
FT2232HL chip
• SiFive CorePlex in silicon
• IQ-Analog NanoRisc5 on FPGA
• Rocket Chip implementation
• gdb and OpenOCD code
• Black box testsuite
• More Information
• Debug list at
https://riscv.org/mailing-lists/
Syntacore RISC-V cores demos
Alexander Redkin
5th RISC-V workshop
Nov 29-30 2016
[email protected]
www.syntacore.com
Syntacore introduction
IP company
1. Develops and licenses energy-efficient programmable cores
With RISC-V ISA
2. Full service to specialize these for the customer needs
Workload analysis/characterization
Workload-specific customization
with tools/compiler support
IP hardening at the required library node
SoC integration and SW migration support
2
Baseline SCRx cores
SCRx: a family of the state-of-the art RISC-V compatible
synthesizable processor cores
SCR1: RV32IC[EM]
SCR3: RV32IMC[E] <= demo
SCR4: RV32IMCF[D]
SCR5: RV[32|64]IM[A]CFD <=demo
Stable, configurable, available for evaluation
Baseline: every core can be extended/customized
3
Thank you!
4
ASIP Designer - Automating ASIP Design
Architecture Definition, Optimization, and Implementation
User-Defined
Algorithms
User-Defined
Architecture
Algorithms
Processor Model
nML
nML
• ASIP Designer creates full SDK
– Compiler-in-the-loop optimization
C
1
Architectural Optimization and
Software Development
3
ASIP Synthesis
RTL Generator
Optimizing C Compiler
FMT
ALU
Instruction
FMT Model
MPY
Set RISC-V
FMT
OPD
2
OPD
SH
RTL Refinement
1
SDK Generation
2
Architectural Optimization
3
HW Generation
1
Link
Synthesizable RTL
OPD
Architecture Refinement
© 2016 Synopsys, Inc.
Asm
VHDL/Verilog
Binary
Debugger &
Profiler
Instruction Set
Simulator
RTL
Simulator
RTL
Synthesizer
• Process starts with pre-existing
example models
– RISC-V Starting point
• ASIP Designer generates
synthesizable RTL
– Performance/Power/Area
• Analysis seeds
refinement/optimization
– ASIP model is refined
– SDK is automatically adapted
– All elements stay in-sync
ASIC
FPGA
SHAVE: Software/Hardware
Assurance Verified End-to-End
•
Create practical, end-to-end assurance cases for mission
critical software/hardware systems that run on COTS hardware.
•
Case study: implement a crypto extension to RISC-V (like AESNI), build a thin firmware layer and small application on top,
and create an assurance case.
Sponsored by the Air Force Research Laboratory (AFRL) and developed with funding from the Defense Advanced
Research Projects Agency (DARPA) under contract number FA8650-16-C-7665. Any views, opinions, findings,
conclusions and/or recommendations expressed in this material are those of the author(s) and do not necessarily
reflect the views of the United States Air Force, the Department of Defense or the U.S. Government.
LibreChainEDA
Open Source IC Design Tool Flow Scripts
Complete FOSS from concept to FPGA
100% Open Source EDA Tools
IP-Xact based tool flows
Design for Reuse best practices
One stop shopping for installation