EE595
Part V
Behavioral Modeling in VHDL
EE 595 EDA / ASIC Design Lab
Behavioral Modeling in VHDL
„
VHDL behavior
„
„
Sequential Statements
Concurrent Statements
EE 595 EDA / ASIC Design Lab
VHDL Behavior
begin
begin
statement
statement
statement
statement
statement
statement
end
EE 595 EDA / ASIC Design Lab
end
VHDL Behavior (cont’d)
„
„
„
„
In this section, some of the most commonly used concurrent and
sequential statements will be introduced.
VHDL provides concurrent statements for parallel operations or
abstract models for a circuit in a behavioral manner. These
statements can be executed by a simulator at the same
simulation time.
The process statement is the primary concurrent statement in
VHDL.
Within the process, sequential statements define the step-bystep behavior of the process.
EE 595 EDA / ASIC Design Lab
VHDL Behavior (cont’d)
„
„
„
„
The process contains sequential statements that describe the
behavior of an architecture.
Sequential statements, define algorithms for the execution
within a process or
a subprogram.
Familiar Notations of
„ sequential flow
„ Control
„ Conditionals
„ Iterations
Executed in order in which they appear in the process (like in a
programming language.)
EE 595 EDA / ASIC Design Lab
Sequential Statements
„
Sequential Statements
„
„
„
„
„
„
„
„
„
„
Variable Assignment Statement
PROCESS Statement (Concurrent and Sequential)
IF Statement
CASE Statement
LOOP Statement
NEXT Statement
EXIT Statement
WAIT Statement
Subprograms
„ Functions
„ Procedures
ASSERT Statement
EE 595 EDA / ASIC Design Lab
Concurrent Statements
„
Concurrent Statements
„
„
„
„
„
Concurrent Signal Assignments
Conditional Signal Assignment
Selected Signal Assignment
Concurrent Procedure Call
BLOCK Statements
„ Guarded Blocks
EE 595 EDA / ASIC Design Lab
Sequential Statements
EE 595 EDA / ASIC Design Lab
Variables
Variable assignment statement
replaces the current value of a variable with a new value which is
Specified by an expression.
target_variable
target_variable:=
:=expression;
expression;
Target_variable is a variable previously declared.
Expression is a statement using variables, signals, and literals.
IMPORTANT :
The named variable and the result of the expression must be same type
Statement executes in zero simulation time
Assignments can be made to a scalar or to an array
Variables declared within a process cannot pass values outside of a
process.
EE 595 EDA / ASIC Design Lab
Variables
Example
character
character:=
:=‘A’
‘A’ ----Character
CharacterAssignment
Assignment
xx:=
:=1.0
1.0
----Real
Realvalue
valueAssignment
Assignment
XX:=
:=1;
1;
YY:=
:=4;
4;
----Integer
IntegerValue
ValueAssignment
Assignment
----Integer
IntegerValue
ValueAssignment
Assignment
ZZ:=
:=XX++Y;
Y;
----Variable
VariableAssignment
Assignmentspecified
specified
----by
byan
anexpression
expression
Note: Recall that signal assignments use the operator “<=“
EE 595 EDA / ASIC Design Lab
Processes
„
„
„
Basic unit of Behavioral Description, found in architectures and
occasionally entities. Entities can only contain passive process
(processes that do not make assignment to signals)
Process statements as a whole are concurrent statements.
Concurrent signal assignment statements are an allowed
shorthand method of writing processes.
Processes have a declaration and statement section. The
statement section contains only sequential statements.
Sequential signal assignments have special considerations.
EE 595 EDA / ASIC Design Lab
Processes (cont’d)
„
„
„
„
„
Variables, constants, data types, and subprograms may be
declared in processes, but not signals.
Anything declared in the entity (e.g.. generics and ports) and the
architectures are visible to processes.
Processes must contain either a wait statement or sensitivity list
(or would never quit running)
During initialization the simulator executes each process up to
its first statement
All processes begin execution during simulator initialization.
Variables are initialized once and thereafter retain their relative
values.
EE 595 EDA / ASIC Design Lab
Parallel Process Execution
X: process begin
if true then
wait...
case expression
........
Y:process begin
... -- Sequential Statements
wait ...
.... --More statements
end process;
end process;
„
„
„
„
VHDL permits concurrent process operation to be simulated.
Each process starts at begin, executes statements in sequence until a wait statement suspends
the process. This allows other processes to run.
When process hits end process; it continues from beginning.
The process label (e.g: A:) helps during simulation and debugging
EE 595 EDA / ASIC Design Lab
Process Model
Process
Signal
Signal
Process
Local
LocalVariable
Variable
Signal
Local
LocalVariable
Variable
Architecture
EE 595 EDA / ASIC Design Lab
Wait for an event (change)
on incoming signals.
then
starts executing all other
sequential statements
in the process
Signal
Process Model (cont’d)
Architecture
Next: Process
First: Process
Done_First
Local
LocalVariable
Variable
Signal
Local
LocalVariable
Variable
All other sequential, and concurrent
statements
1. Signals must be used to communicate between processes.
2. Variables are local to the process in which they are declared.
3. Signals can be used to synchronize processes.
EE 595 EDA / ASIC Design Lab
Communication Between
Processes via Signals
architecture
architectureEXAMPLE
EXAMPLEofofCOMMUNICATE
COMMUNICATEisis
signal
signalDONE_FIRST
DONE_FIRST: :Bit
Bit:=:=‘0’;
‘0’;
begin
begin
FIRST:
FIRST:process
process
begin
begin
......
----do
......
dofirst
firststeps......
steps......
DONE_FIRST
DONE_FIRST<=
<=‘1’;
‘1’;
wait
waitfor
for10
10ns;
ns;
end
process;
end process;
NEXT:
NEXT:process
process
begin
begin
wait
waituntil
untilDONE_FIRST
DONE_FIRST==‘1’;
‘1’;
.......
----do
.......
dothe
theother
othersteps
steps
end
process;
end process;
end
endEXAMPLE;
EXAMPLE;
EE 595 EDA / ASIC Design Lab
Declaration of
the signal
Assignment
Other process waits
until ‘1’ is assigned
to the signal
Signals Communicate in
Between the Processes
Concurrent
ConcurrentStatements
Statementsare
are
evaluated
evaluatedfirst
firstuntil
untilto
toaa“wait”
“wait”
When
Whenall
allthe
theprocesses
processesare
arewaiting,
waiting,
all
allthe
thesignals
signalspropagate.
propagate.
EE 595 EDA / ASIC Design Lab
Signals Assigned After
Processes Run
Process 1
Uses old values
of signals
Process 2
Uses old values
of signals
Process 3
Process 1
Signal
assignments with
Zero delay
Process 2
Signal
assignments with
Zero delay
Process 5
Process 3
Uses old values
of signals
Signal
assignments with
Zero delay
All
Allprocesses
processesrun
run
until
untilaa“wait”
“wait”
executed
executed
All
Allprocesses
processesare
are
“waiting
“waiting
EE 595 EDA / ASIC Design Lab
Process 4
Some
Someother
other
processes
processeswoken
wokenup
up
Process
Example
entity NAND2 is
Port (A, B: in Bit;
C:
out Bit)
end NAND2;
architecture BEHAVE of NAND2 is
PDQ : process
variable TEMP : Bit;
begin
Process will suspend here
wait on A, B;
TEMP := A nand B;
if (TEMP = ‘1’) then
A
B
.......
C
sequential statements
........
end process;
end BEHAVE;
EE 595 EDA / ASIC Design Lab
Process with Signals
„
„
„
„
Contains only sequential statements
Can access signals defined in architecture and entity
Must contain either an explicit sensitivity list, or a wait
statement(s)
Can have variable assignment and signal assignment
statements.
EE 595 EDA / ASIC Design Lab
Sensitivity List
„
„
„
„
PROCESS (sig1, sig2,...sigN)
Events (changes) on any signal in sensitivity list will cause process execution to
resume, after BEGIN statement
Process execution continues until END process statement is reached
For synthesis, all signals which are read, typically must be included in the sensitivity
list.
Sensitivity List
process
process(a,b)
(a,b)
begin
begin
yy<=
<=aaAND
ANDbbAND
ANDc;c;
end
endprocess;
process;
EE 595 EDA / ASIC Design Lab
----the
theprocess
processisisonly
onlysensitive
sensitivetotoa,a,bbany
any
----changes
on
c
does
not
initiates
execution
changes on c does not initiates executionofof
----process
process
Process with Sensitivity List
Example
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_1164.all;
TEMP
entity NAND2 is
entity NAND2 is
port(
A,B : in
std_logic;
port(
A,B : in
std_logic;
C: out
std_logic);
C: out
std_logic);
end NAND2;
end NAND2;
architecture NAND2 of NAND2 is
architecture NAND2 of NAND2 is
begin
begin
process (a,b)
-- signals a, b are the sensitivity list
process (a,b)
-- signals a, b are the sensitivity list
variable TEMP : std_logic;
variable TEMP : std_logic;
begin
begin
TEMP := not (A and B);
TEMP := not (A and B);
if (TEMP = ‘1’) then c <= TEMP after 6 ns; -- sequential signal assignment
if (TEMP = ‘1’) then c <= TEMP after 6 ns; -- sequential signal assignment
elsif (TEMP = ‘0’) then C <= TEMP after 5 ns;
elsif (TEMP = ‘0’) then C <= TEMP after 5 ns;
else C <= TEMP after 6 ns;
else C <= TEMP after 6 ns;
end if;
end if;
end process;
end process;
end NAND2;
end NAND2;
A
B
EE 595 EDA / ASIC Design Lab
C
IF statement
„
IF statements
„ Represent hardware decoders in both abstract and detailed hardware models
„ Select for execution one or more of the enclosed sequential statements
(if more than one sequential statement, use ‘;’ at the end of each statement).
„ Can be nested.
ififCONDITION1
CONDITION1then
thenSequential_Statement(s);
Sequential_Statement(s);
{elsif
CONDITION2
{elsif CONDITION2then
thenSequential_Statement(s);}
Sequential_Statement(s);}
{elsif
CONDITION3
then
Sequential_Statement(s);}
{elsif CONDITION3 then Sequential_Statement(s);}
{elsif
{elsifCONDITION4
CONDITION4then
thenSequential_Statement(s);}
Sequential_Statement(s);}
{......
{......
}}
[else
[elseSequential_Statement(s);]
Sequential_Statement(s);]
end
if;
end if;
EE 595 EDA / ASIC Design Lab
IF statement (cont’d)
ififCONDITION
CONDITIONthen
then
.....
.....
end
endif;if;
---- Sequential_Statement(s)
Sequential_Statement(s)
if CONDITION then
if CONDITION then
.....
.....
else
else
.....
.....
end
if;
end if;
-- Sequential_Statement(s)
-- Sequential_Statement(s)
-- Sequential_Statement(s)
-- Sequential_Statement(s)
ififCONDITION1
CONDITION1then
then
.....
---- Sequential_Statements
.....
Sequential_Statements
elsif
CONDITION2
elsif CONDITION2then
then
.....
---- Sequential_Statement(s)
.....
Sequential_Statement(s)
elsif
CONDITION3
then
elsif CONDITION3 then
.....
---- Sequential_Statement(s)
.....
Sequential_Statement(s)
else
else
.....
---- Sequential_Statement(s)
.....
Sequential_Statement(s)
end
endif;if;
EE 595 EDA / ASIC Design Lab
IF statement
Example
library
libraryIEEE;
IEEE;
use
IEEE.Std_uLogic_1164.all;
use IEEE.Std_uLogic_1164.all;
entity
entityIF_STATEMENT
IF_STATEMENTisis
port
U,U,W,
port( (
W,X,X,Y:Y:ininstd_ulogic_vector
std_ulogic_vector(1(1downto
downto0);
0);
ZZ
: :out
std_ulogic_vector
(1
downto
out std_ulogic_vector (1 downto0));
0));
end
IF_STATEMENT;
end IF_STATEMENT;
architecture
architectureIF_ARC
IF_ARCofofIF_STATEMENT
IF_STATEMENTisis
begin
begin
process
process(U,
(U,W,
W,X,X,Y)Y)
begin
begin
ifif( (YY==“00”)
“00”)then
then
ZZ<=
<=U;U;
elsif
(Y
=
“01”)
then
elsif (Y = “01”) then
ZZ<=
<=W;
W;
else
else
ZZ<=
<=X;X;
end
endif;if;
end
process;
end process;
end
endIF_ARC;
IF_ARC;
EE 595 EDA / ASIC Design Lab
IF statement
Example (cont’d)
---library
libraryIEEE;
IEEE;
use
IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_1164.all;
use
useIEEE.NUMERIC_STD.all;
IEEE.NUMERIC_STD.all;
entity
entityCOUNT16
COUNT16IsIs
port
port(CLK,RST,LOAD:
(CLK,RST,LOAD:ininstd_ulogic;
std_ulogic;
DATA:
in
unsigned
(3
downto
DATA: in unsigned (3 downto0);0);
COUNT:
COUNT:out
outunsigned
unsigned(3(3downto
downto0)0)
););
end
endCOUNT16;
COUNT16;
Note:
Rising Edge is recognized by simulation tool only,
not by synthesis tool.
EE 595 EDA / ASIC Design Lab
architecture
architectureCOUNT16_A
COUNT16_AofofCOUNT16
COUNT16IsIs
begin
begin
process(RST,CLK)
process(RST,CLK)
variable
variableQ:Q:unsigned
unsigned(3(3downto
downto0);0);
begin
begin
ififRst
Rst=='1''1'then
then
QQ:=:="0000";
"0000";
elsif
elsifrising_edge(CLK)
rising_edge(CLK)then
then
ififLOAD
=
'1'
then
LOAD = '1' then
QQ:=:=DATA;
DATA;
elsif
Q
=
elsif Q =1515then
then
QQ:=:="0000";
"0000";
else
else
QQ:=:=QQ++"0001";
"0001";
end if;
end if;
end if;
end if;
COUNT <= Q;
COUNT <= Q;
end process;
end process;
end COUNT16_A;
end COUNT16_A;
IF statement
Example (cont’d)
ifif( (U)
U)then
then ZZ<=
<=VALUE_1;
VALUE_1;
elsif
(W)
elsif (W)then
thenZZ<=
<=VALUE_2;
VALUE_2;
elsif
(X)
elsif (X) then
then ZZ<=
<=VALUE_3;
VALUE_3;
end
if;
end if;
(ALWAYS)
(ALWAYS)EQUAL
EQUAL
ifif( (X)
X) then
then ZZ<=
<=VALUE_3;
VALUE_3;
end
if;
end if;
ifif(W)
(W) then
then ZZ<=
<=VALUE_2;
VALUE_2;
end
if;
end if;
ifif(U)
(U) then
then ZZ<=
<=VALUE_1;
VALUE_1;
end
if;
end if;
EE 595 EDA / ASIC Design Lab
NOT
NOT(ALWAYS)
(ALWAYS)EQUAL
EQUAL
ifif( (U)
U) then
then ZZ<=
<=VALUE_1;
VALUE_1;
end
if;
end if;
ifif(W)
(W) then
then ZZ<=
<=VALUE_2;
VALUE_2;
end
if;
end if;
ifif(X)
(X) then
then ZZ<=
<=VALUE_3;
VALUE_3;
end
if;
end if;
CASE statement
„
CASE statements
„ useful to describe decoding of busses and other codes
„ Select for execution one of a number of alternative sequential statements
(if more than one sequential statement, use ‘;’ at the end of each
statement).
case
case(EXPRESSION)
(EXPRESSION)isis
when
whenCHOISE1
CHOISE1=>
=>Sequential_Statement(s);
Sequential_Statement(s);
when
CHOISE2
|
CHOISE3
when CHOISE2 | CHOISE3| |CHOISE4
CHOISE4=>
=>Sequential_Statement(s);
Sequential_Statement(s);
when
value1
to
value2
=>
Sequential_Statement(s);
when value1 to value2 => Sequential_Statement(s);
when
whenothers
others=>
=>Sequential_Statement(s);
Sequential_Statement(s);
end
case;
end case;
EE 595 EDA / ASIC Design Lab
CASE statement
Example
library
libraryIEEE;
IEEE;
use
IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_1164.all;
entity
entityCASE_STATEMENT
CASE_STATEMENTisis
port
U,U,W,
port( (
W,X,X,Y:Y:inininteger
integerrange
range00toto15;
15;
ZZ
: :out
integer
range
0
out integer range 0toto15);
15);
end
CASE_STATEMENT;
end CASE_STATEMENT;
architecture
architectureCASE_ARC
CASE_ARCofofCASE_STATEMENT
CASE_STATEMENTisis
begin
begin
process
process(U,
(U,W,
W,X,X,Y)Y)
begin
begin
case
caseYYisis
when
when00toto99 =>
=>ZZ<=
<=X;X;
when
13
=>
Z
<=
when 13
=> Z <=W;
W;
when
when11
11| |15=>
15=>ZZ<=
<=U;U;
when
whenothers
others=>
=>ZZ<=
<=0;0;
end
endcase;
case;
end
process;
end process;
end
IF_ARC;
end IF_ARC;
EE 595 EDA / ASIC Design Lab
CASE statement (cont’d)
„
Rules
„
„
„
Use the CASE statement, when you have a complex decoding situation
(It is more readable than nested if statements.)
CASE statement must enumerate all possible values of the expression or
to have an OTHERS clause as a last choice of all of the choices.
None of the choices may overlap.
case BCD_DECODER is
case BCD_DECODER is
when “0000” => SEGMENTS := “1111110”; -- zero
when “0000” => SEGMENTS := “1111110”; -- zero
when “0001” => SEGMENTS := “1100000”; -- one
when “0001” => SEGMENTS := “1100000”; -- one
when “0010” => SEGMENTS := “1011011”; -- two
when “0010” => SEGMENTS := “1011011”; -- two
when “0011” => SEGMENTS := “1110011”; -- three
when “0011” => SEGMENTS := “1110011”; -- three
when “0100” => SEGMENTS := “1100101”; -- four
when “0100” => SEGMENTS := “1100101”; -- four
when “0101” => SEGMENTS := “0110111”; -- five
when “0101” => SEGMENTS := “0110111”; -- five
when “0110” => SEGMENTS := “0111111”; -- six
when “0110” => SEGMENTS := “0111111”; -- six
when “0111” => SEGMENTS := “1100010”; -- seven
when “0111” => SEGMENTS := “1100010”; -- seven
when “1000” => SEGMENTS := “1111111”; -- eight
when “1000” => SEGMENTS := “1111111”; -- eight
when “1001” => SEGMENTS := “1110111”; -- nine
when “1001” => SEGMENTS := “1110111”; -- nine
when OTHERS
=> SEGMENTS := “- - - - - - -”; -- don’t care
when OTHERS
=> SEGMENTS := “- - - - - - -”; -- don’t care
end case;
end case;
EE 595 EDA / ASIC Design Lab
6
5
7
4
1
2
3
LOOP statement
„
LOOP Statements
„ Provide a convenient way to describe bit-sliced logic or iterative circuit
behavior.
„ Include sequential statements to execute repeatedly, zero or more times.
„ Can be nested.
OR
OR
[LOOP_LABEL]:
[LOOP_LABEL]:while
whileCONDITION1
CONDITION1loop
loop
.....
-Sequential_Statement(s)
.....
-- Sequential_Statement(s)
end
loop[LOOP_LABEL];
end loop[LOOP_LABEL];
[LOOP_LABEL]:
[LOOP_LABEL]:for
forIDENTIFIER
IDENTIFIERininDISCRETE_RANGE
DISCRETE_RANGEloop
loop
.....
-Sequential_Statement(s)
.....
-- Sequential_Statement(s)
end
loop[LOOP_LABEL];
end loop[LOOP_LABEL];
EE 595 EDA / ASIC Design Lab
LOOP statements
Example
FOR LOOP
LABEL_ONE:
LABEL_ONE: for
forI Iinin11toto20
20loop
loop
Sequential_Statement(s);
Sequential_Statement(s);
end
endloop
loopLABEL_ONE
LABEL_ONE
WHILE LOOP
INITIAL
INITIAL:=:=0;0;
LABEL_TWO:
LABEL_TWO: while
while(INITIAL
(INITIAL<<10)
10)loop
loop
Sequential_Statement(s);
Sequential_Statement(s);
INITIAL
INITIAL:=:=INITIAL
INITIAL++1;1;
end
endloop
loopLABEL_TWO
LABEL_TWO
EE 595 EDA / ASIC Design Lab
LOOP statements
Example (cont’d)
LABEL_THREE:
LABEL_THREE:for
forI Iinin11toto10
10loop
loop
VALUE
VALUE:=:=I I**2;2;
SQUARE_I(I)
SQUARE_I(I):=:=I I**I;I;
end
endloop
loopLABEL_THREE;
LABEL_THREE;
Loop index “I”
• is not a variable
• Hides any other “I” not in the loop
• cannot be seen outside the loop
• must be a discrete type (not REAL)
• can be used as array reference
LABEL_FOUR:
LABEL_FOUR:while
while(TODAY
(TODAY<=
<=5)5)loop
loop
----weekday
weekdaySequential_Statements
Sequential_Statements
TODAY
TODAY:=:=TODAY
TODAY++1;1;
end
endloop
loopLABEL_FOUR;
LABEL_FOUR;
EE 595 EDA / ASIC Design Lab
NEXT statement
„
The NEXT statement
„ skip the execution to the next iteration of an enclosing LOOP statement.
„ is convenient to use when you want to skip an iteration of a LOOP.
next
next[LABEL]
[LABEL][when
[whenCONDITION];
CONDITION];
EE 595 EDA / ASIC Design Lab
NEXT statement
Example
for
forI Iinin11toto30
30loop
loop
ifif(VALUE(I)
(VALUE(I)==0)0)then
thennext;
next;
end
if;
end if;
OUTPUT_VALUE(I)
OUTPUT_VALUE(I):=:=VALUE(I);
VALUE(I);
end
loop;
end loop;
The loop statement has a range bounded by the end loop. Execution of the next statement
causes iteration to skip to the next loop index value (e.g. for I.)
LABEL1:
LABEL1:while
whileI I<<20
20loop
loop
LABEL2:
LABEL2:while
whileJJ<<20
20loop
loop
.....
.....
.....
----Sequential_Statement(s);
.....
Sequential_Statement(s);
.....
.....
next
nextLABEL2
LABEL2when
whenI I==J;J;
.....
.....
.....
----Sequential_Statement(s);
.....
Sequential_Statement(s);
.....
.....
end
endloop
loopLABEL2;
LABEL2;
end
loop
LABEL1;
end loop LABEL1;
EE 595 EDA / ASIC Design Lab
Nested loops should
be given unique labels.
EXIT statement
„
„
The EXIT statement completes the execution of an enclosing LOOP
statement.
The LOOP label in the EXIT statement identifies the particular loop to be
exited.
exit
exit[LABEL]
[LABEL][when
[whenCONDITION];
CONDITION];
EE 595 EDA / ASIC Design Lab
EXIT statement
Example
for
forI Iin
in11to
to30
30loop
loop
ifif(VALUE(I)
(VALUE(I)==0)
0)then
thenexit;
exit;
end
if;
end if;
OUTPUT_VALUE(I)
OUTPUT_VALUE(I):=:=VALUE(I);
VALUE(I);
end
endloop;
loop;
The for statement has a range for loop. When the I indexed
variable has a value of zero, exit causes execution to exit the loop
entirely.
EE 595 EDA / ASIC Design Lab
WAIT statement
„
The WAIT statement
„
„
„
„
provides for modeling signal-dependent activation
can be used to model a logic block that is activated by one or more signals.
causes a simulator to suspend execution of a process statement or a procedure,
until some conditions are met, then execution resumes.
forces simulator signal propagation.
wait
wait
wait
waiton
onSIGNAL_NAME;
SIGNAL_NAME;
wait
until
wait untilTRUE_CONDITION;
TRUE_CONDITION;
wait
waitfor
forTIME_EXPRESSION;
TIME_EXPRESSION;
Processes with no sensitivity list, no wait statement will loop forever at the initialization
EE 595 EDA / ASIC Design Lab
WAIT statement
Example
wait
waiton
onA,B;
A,B;
suspends execution until a change occur on
either signal A or B. Same as Process (A,B)
wait
waituntil
untilTT>>10;
10;
suspends execution until condition T > 10 becomes
satisfied. It requires an event on T to evaluate the
expression.
wait
waitfor
for20
20ns;
ns;
EE 595 EDA / ASIC Design Lab
suspends execution of process for 20 ns.
ASSERT statement
„
Assert statement allows for testing a condition or error message. It checks to
determine if a specified condition is true, and displays a message if a condition
is false.
assert
assertCONDITION
CONDITION[report
[reportMESSAGE_STRING]
MESSAGE_STRING][severity
[severityMESSAGE_STRING];
MESSAGE_STRING];
Severity Levels are
Note, Warning, Error, Failure
EE 595 EDA / ASIC Design Lab
ASSERT statement (cont’d)
„
Assert statement
„ Cannot be formatted
„ Can be used as either concurrent or sequential statements
„ Prints out
„ simulation time
„ user written string
„ instance name
„ severity level (Defaults to ERROR)
„ Useful for timing checks, range checks, debugging.
EE 595 EDA / ASIC Design Lab
ASSERT statement
Example
library
libraryIEEE;
IEEE;
use
IEEE.std_logic_1164.all;
use IEEE.std_logic_1164.all;
Passive Process
entity
SETUP_CHECK
is
entity SETUP_CHECK is
port
D,
port( (
D,CLK:
CLK:in
instd_logic;
std_logic;
Q:
Q:out
outstd_logic);
std_logic);
begin
begin
SETUP_CHECK_PROCESS:
SETUP_CHECK_PROCESS:process
process(CLK)
(CLK)
begin
begin
ifif(CLK=‘1’)
(CLK=‘1’)and
and(CLK’LAST_VALUE
(CLK’LAST_VALUE=‘0’)
=‘0’)then
then
assert
assert(D’LAST_EVENT
(D’LAST_EVENT>=
>=33ns)
ns)
report
report“Setup
“SetupError”
Error”
severity
WARNING;
severity WARNING;
end
if;
end if;
end
endprocess;
process;
end
endSETUP_CHECK;
SETUP_CHECK;
EE 595 EDA / ASIC Design Lab
Aliases
„
„
„
Alternate designation for an object (signal, variable, constant)
Assignments to the alias are assignments to the object. Assignments to the
object are assignments to the alias.
Example:
signal
signalinstruction
instruction: :std_logic_vector
std_logic_vector(15
(15DOWNTO
DOWNTO0);
0);
alias
aliasinst
inst: :std_logic_vector
std_logic_vector(15
(15DOWNTO
DOWNTO0)
0)isisinstruction;
instruction;
alias
aliasreverse_inst
reverse_inst: :std_logic_vector
std_logic_vector(0
(0TO
TO15)
15)isisinstruction;
instruction;
alias
aliasopcode
opcode: :std_logic_vector
std_logic_vector(3
(3DOWNTO
DOWNTO0)
0)isisinstruction
instruction
(15
(15DOWNTO
DOWNTO12);
12); --slice
--slice
alias
--alias
aliasopbit
opbit: :std_logic
std_logicisisopcode(0);
opcode(0);
--aliasofofan
analias
alias
EE 595 EDA / ASIC Design Lab
Aliases (cont’d)
signal
signalINST_FIELD
INST_FIELD: :Bit_vector(31
Bit_vector(31downto
downto0);
0);
alias
aliasOP_FIELD:Bit_vector(3
OP_FIELD:Bit_vector(3downto
downto0)0)isis
INST_FIELD(31
INST_FIELD(31downto
downto28);
28);
INST_FIELD<=010001010110011110001001101010110
OP_FIELD <= 0100
EE 595 EDA / ASIC Design Lab
Subprograms
„
„
„
„
A subprogram has sequential statements contained inside, and is
called from a process. Subprograms provide a convenient way of
documenting frequently used operations.
There are two different types of subprograms
„ A procedure (Return Multiple Values)
„ A function (Return a Single Value)
Typical usage areas
„ Conversion Functions
„ Resolution Functions
Subprograms are either built-in or user-designed.
EE 595 EDA / ASIC Design Lab
Subprograms (cont’d)
„
„
„
„
„
„
„
„
Contain sequential statements similar to processes
May declare local variables, constants
Executed when called from a sequential statement.
Local Variables are re-initialized every time a subprogram is called.
Parameters of calling routine are known as actuals, while the parameters of
the declared subprogram are known as formals.
Up level referencing to higher level variables and signals is allowed.
Recursive calls by functions and procedures are allowed
Attributes of signals cannot be accessed within subprograms
EE 595 EDA / ASIC Design Lab
Functions
A user defined function needs to be declared if it is called. When a function is called,
values are passed in through parameters just prior to its execution.
process
process
function
functionC_TO_F
C_TO_F(C:
(C:real)
real)return
returnreal
realisis
variable
variableF:F:real;
real;
begin
begin
FF:=:=CC* *9.0
9.0/ /5.0
5.0++32.0;
32.0;
return
(F);
return (F);
end
C_TO_F;
end C_TO_F;
variable
variableNEW_TEMP:
NEW_TEMP:real;
real;
begin
begin
NEW_TEMP
NEW_TEMP:=:=C_TO_F
C_TO_F(5.0)
(5.0)++20.0;
20.0;
.....
-Sequantial_Statement(s);
.....
-- Sequantial_Statement(s);
end
process;
end process;
EE 595 EDA / ASIC Design Lab
Function
Declaration
Function
Declaration
Functions (cont’d)
function
functionNAME
NAME(PARAMETER)
(PARAMETER)return
returnTYPE
TYPEisis
.....
..... ----variable
variabledeclarations
declarations
begin
begin
.....
.....
.....
..... --Sequential_
--Sequential_Statements
Statements
.....
.....
return
return( ( ););
end
endNAME;
NAME;
„
„
„
„
„
Function contains sequential statements
Converts one type to another
Some built-in functions
Some user supplies and reuse.
No side effects
EE 595 EDA / ASIC Design Lab
Functions (cont’d)
type
----Incoming
typeFOURVAL
FOURVALisis(‘X’,
(‘X’,‘L’,
‘L’,‘H’,
‘H’,‘Z’);
‘Z’);
Incomingvalues
values
type
----Outgoing
typeVALUE4
VALUE4isis(‘X’,
(‘X’,‘0’,
‘0’,‘1’,
‘1’,‘Z’);
‘Z’);
Outgoingvalues
values
function
functionCONVER4VAL
CONVER4VAL(S:
(S:FOURVAL)
FOURVAL)return
returnVALUE4
VALUE4isis
begin
begin
case
caseSSisis
when
when‘X’
‘X’=>
=>return
return‘X’;
‘X’;
when
when‘L’‘L’=>
=>return
return‘0’;
‘0’;
when
when‘H’
‘H’=>
=>return
return‘1’;
‘1’;
when
when‘Z’
‘Z’=>
=>return
return‘Z’;
‘Z’;
end
endcase;
case;
end
endCONVER4VAL;
CONVER4VAL;
process
process
begin
begin
TYPE
TYPECONVERSION
CONVERSION
variable
variablePDQ:
PDQ:FOURVAL;
FOURVAL;
variable
variableXYZ:
XYZ:VALUE4;
VALUE4;
XYZ
XYZ:=:=CONVER4VAL
CONVER4VAL(PDQ)
(PDQ)
end
process;
end process;
EE 595 EDA / ASIC Design Lab
----function
functioncall
call
Functions (cont’d)
„
„
„
„
Called by expressions
Produce a single return value
Can not modify the parameters passed to it
Requires a RETURN statement
function
functionADD_BITS
ADD_BITS(A,
(A,BB: :ininbit)
bit)return
returnBit
Bitisis
begin
begin ----functions
functionscan
canNOT
NOTreturn
returnmultiple
multiplevalues
values
return
(A
XOR
B);
return (A XOR B);
end
ADD_BITS;
end ADD_BITS;
function
functionADD_BITS2
ADD_BITS2(A,
(A,BB: :ininBit)
Bit)return
returnBit
Bitisis
variable
variableRESULT
RESULT: :bit;
bit; ----variable
variableisislocal
localtotofunction
function
begin
begin
RESULT
RESULT:=:=(A
(AXOR
XORB);
B);
return
RESULT;
-the
return RESULT; -- thetwo
twofunctions
functionsare
areequivalent
equivalent
end
ADD_BIT2;
end ADD_BIT2;
EE 595 EDA / ASIC Design Lab
Functions (cont’d)
architecture BEHAVIOR of ADDER is
begin
process (ENABLE, X, Y)
begin
if (ENABLE = '1') then
RESULT <= ADD_BITS(X, Y);
CARRY <= X and Y;
else
CARRY, RESULT <= '0';
end process;
end BEHAVIOR;
„
„
function
functionADD_BITS
ADD_BITS
Functions must be called by other statements
Parameters use positional association
EE 595 EDA / ASIC Design Lab
(A,
(A,BB: :in
inBit)
Bit)
Functions
Example
----Convert
Convertaastd_ulogic_vector
std_ulogic_vectortotoan
anunsigned
unsignedinteger
integer
---function
functionTO_UNSIGNED
TO_UNSIGNED(A:
(A:std_ulogic_vector)
std_ulogic_vector)return
returninteger
integerisis
alias
aliasAV:
AV:std_
std_ulogic_vector
ulogic_vector(1(1totoA'LENGTH)
A'LENGTH)isisA;
A;
variable
RET,D:
integer;
variable RET,D: integer;
begin
begin
DD:=:=1;1;
RET
RET:=:=0;0;
for
forI IininA'LENGTH
A'LENGTHdownto
downto11loop
loop
ifif(AV(I)
=
'1')
then
(AV(I) = '1') then
RET
RET:=:=RET
RET++D;
D;
end
if;
end if;
DD:=:=DD* *2;2;
end
endloop;
loop;
return
returnRET;
RET;
END
TO_UNSIGNED;
END TO_UNSIGNED;
EE 595 EDA / ASIC Design Lab
Functions
Example (cont’d)
----Convert
Convertan
aninteger
integertotoaastd_ulogic_vector
std_ulogic_vector
---function
functionTO_VECTOR
TO_VECTOR(SIZE:
(SIZE:integer;
integer;NUM:
NUM:integer)
integer)return
returnstd_ulogic_vector
std_ulogic_vectorisis
variable
variableRET:
RET:std_ulogic_vector
std_ulogic_vector(1(1to
toSIZE);
SIZE);
variable
A:
integer;
variable A: integer;
begin
begin
AA:=:=NUM;
NUM;
for
I
in
for I inSIZE
SIZEdownto
downto11loop
loop
ifif((A
mod
2)
=
1)
then
((A mod 2) = 1) then
RET(I)
RET(I):=:='1';
'1';
else
else
RET(I)
RET(I):=:='0';
'0';
end
if;
end if;
AA:=:=AA/ /2;2;
end
endloop;
loop;
return
returnRET;
RET;
end
TO_VECTOR;
end TO_VECTOR;
EE 595 EDA / ASIC Design Lab
Procedures
„
„
„
„
„
Assignments can be made to as many as desired - assignments are
made to parameters of modes OUT or INOUT
Side effects - assignments can be made to signals which are not in the
parameter, but only if the procedure is declared inside of the process
that calls it.
Static Up Level referencing - reference variable(s) from the process or
other procedures that called them. If the variable(s) are not include in
parameter list they may not be assigned to.
Concurrent procedures calls are execute once at initialization and then
execute only when the parameters of mode IN or INOUT have events
on them.
Invocation is a statement.
EE 595 EDA / ASIC Design Lab
Procedures (cont’d)
function
functionNAME
NAME(PARAMETERS)
(PARAMETERS)isis
.....
..... ----[variable]
[variable]
.....
-[constants]
..... -- [constants]
.....
..... ----[types]
[types]
.....
-[declarations]
..... -- [declarations]
begin
begin
.....
.....
.....
..... --Sequential_Statements
--Sequential_Statements
.....
.....
return
return( ( ););
end
endNAME;
NAME;
PARAMETERS
variable NAMES [in | out | inout] type [:= EXPRESSION];
or
signal NAMES [in | out | inout] TYPE;
EE 595 EDA / ASIC Design Lab
Procedures (cont’d)
„
Procedure Declaration
procedure
procedureP;
P;
procedure
procedureXOR2
XOR2( ( signal
signalIN1,
IN1,IN2
IN2: :in
inBit;
Bit;
signal
OUT1
:
out
Bit);
signal OUT1 : out Bit);
----use
word
‘signal’
is
use word ‘signal’ isoptional
optionalfor
forparameters
parametersofofmode
modein,
in,but
but
----required
if
out
parameter
is
a
signal
required if out parameter is a signal
„
Procedure Body
procedure
procedureDIV_16
DIV_16(A
(A: :inout
inoutinteger)
integer)isis
begin
begin
AA:=:=A/16;
A/16;
end
DIV_16;
end DIV_16;
EE 595 EDA / ASIC Design Lab
Procedures
Example
Actuals in Call
architecture
architectureBEHAVIOR
BEHAVIORof
ofADDER
ADDERisis
begin
begin
process
process(ENABLE,
(ENABLE,X,
X,Y)
Y)
begin
begin
ADD_BITS3(X,
ADD_BITS3(X,Y,
Y,ENABLE,
ENABLE,
RESULT,
RESULT,CARRY);
CARRY);
end
process;
end process;
end
BEHAVIOR;
end BEHAVIOR;
z
The parameters must be compatible
in terms of data flow and data type
EE 595 EDA / ASIC Design Lab
z
With parameter passing, it is
possible to further simplify the
architecture
Formals in
Declaration
procedure
procedureADD_BITS3
ADD_BITS3
(signal
(signalA,
A,B,
B,EN
EN: :ininBit;
Bit;
signal
TEMP_RESULT,
signal TEMP_RESULT,
TEMP_CARRY
TEMP_CARRY: :out
outBit);
Bit);
Procedures
Example (cont’d)
Procedure for 8 bit parity generator
procedure
procedure PARITY
PARITY(A
(A: :in
inBit_vector
Bit_vector(0
(0to
to7);
7);
RESULT,
RESULT,RESULT_INV:
RESULT_INV:out
outBit)
Bit)isis
variable
variableTEMP:
TEMP:Bit;
Bit;
begin
begin
TEMP
TEMP:=
:=‘0’;
‘0’;
for
forI Iin
in00to
to77loop
loop
TEMP
TEMP:=
:=TEMP
TEMPxor
xorA(I);
A(I);
end
endloop;
loop;
RESULT
RESULT:=
:=TEMP;
TEMP;
RESULT_INV
RESULT_INV:=
:=not
notTEMP;
TEMP;
end
PARITY;
end PARITY;
EE 595 EDA / ASIC Design Lab
Summary
„
„
„
„
„
A process defines regions in architectures where sequential statements
are executed (components are not permitted.)
Process statements provide concurrent processing capability using
local variables and global signals.
VHDL Contains sequential statements, including IF THEN ELSE, CASE
LOOP, etc.
WAIT statements dynamically control process suspension/execution.
In simulation, all processes are started and executed up to a WAIT.
A process can call functions (that return a single value) and procedure
(that return more than one value.)
EE 595 EDA / ASIC Design Lab
Concurrent Statements
EE 595 EDA / ASIC Design Lab
Concurrent Statement
„
„
„
„
Exists outside of a process but in an architecture
The process is itself a concurrent statement all
processes scheduled to run concurrently
Concurrent signal assignment is a short hand form
for a single statement process -- equivalent to
process containing one statement, sensitive to
changes on the right hand side.
Used frequently in DATAFLOW style descriptions.
EE 595 EDA / ASIC Design Lab
The Process
„
A Process
„
Runs concurrently with other processes
„
Contains only sequential statements
„
Defines regions in architectures where statements execute sequentially
„
Must contain either an explicit sensitivity list or a WAIT statement
„
Can access signals defined in architecture and entity.
ONE: Process
-- Sequential
-- Statements
wait...
end;
C
o
n
c
u
r
r
e
n
t
EE 595 EDA / ASIC Design Lab
TWO: Process
-- Sequential
-- Statements
wait...
end;
Concurrent Signal Assignment
„
„
„
Execute asynchronously, with no defined relative order
Used for dataflow style descriptions
Syntax:
TARGET
TARGET<=
<=EXPRESSION;
EXPRESSION;
EXPRESSION is logical, comparative, or arithmetic operation
„
„
„
VHDL offers other forms of Concurrent Signal Assignment:
Conditional - similar to if statements
Selected - similar to case statement
EE 595 EDA / ASIC Design Lab
Concurrent Assignment
Statements
C
architecture
architectureEXAMPLE
EXAMPLE
begin
begin
AA<=
<=BB++C;
C; ----Statement_one
Statement_one
ZZ<=
<=XX++Y;
Y; ----Statement_two
Statement_two
end;
end;
+
A
+
Z
B
X
Y
• Builds combinational circuitry
• Note that
if B or C change then Statement _one is evaluated
if X or Y change then Statement_two is evaluated
EE 595 EDA / ASIC Design Lab
Concurrent Signal Sensitivity
„
„
„
Concurrent Statements are sensitive to all signals on
the input side
If a signal appears on both sides, the statement is
sensitive to changes in its own output.
A <= A+B; will be evaluated when B changes. This
will change A and the statement will be evaluated
again.
Time will not be able to advance because the
statement keeps executing.
EE 595 EDA / ASIC Design Lab
Conditional Signal Statement
A conditional signal assignment is an concurrent statement and has one target,
but can have more than one expression. Only one of the expressions can be
used at a time.
TARGET
TARGET<=
<={EXPRESSION
{EXPRESSIONwhen
whenCONDITION
CONDITIONelse}
else}EXPRESSION;
EXPRESSION;
Example
ZZ<=
<=AAwhen
when(X
(X>>3)
3)else
else
BBwhen
when(X
(X<<3)
3)else
else
C;
C;
Note: You cannot use conditional signal assignment in a process.
EE 595 EDA / ASIC Design Lab
Conditional Signal Statement
Example
entity
entityEXAMPLE
EXAMPLEisis
port
port(A,B,
(A,B,C,
C,SEL
SEL
ZZ
: :inininteger
integerrange
range00toto7;7;
: :out
outinteger
integerrange
range00toto7);
7);
end
endEXAMPLE;
EXAMPLE;
architecture
architectureIF_TYPE
IF_TYPEof
ofEXAMPLE
EXAMPLEisis
begin
begin
process
process(A,
(A,B,
B,C,
C,SEL)
SEL)
begin
begin
architecture
ifif(SEL
architectureCOND_TYPE
COND_TYPEof
ofEXAMPLE
EXAMPLEisis
(SEL>>5)5)then
then
begin
ZZ<=
begin
<=A;
A;
ZZ<<== AAwhen
elsif
(SEL
<
5)
then
whenSEL
SEL>>55else
else
elsif (SEL < 5) then
BBwhen
SEL
<
5
else
ZZ<=
B;
when SEL < 5 else
<= B;
C;
else
C;
else
end
COND_TYPE.
ZZ<=
end COND_TYPE.
<=C;
C;
end
endif;
if;
end
process;
end process;
end
endIF_TYPE;
IF_TYPE;
EE 595 EDA / ASIC Design Lab
Selected Signal Statement
A selected signal assignment statement can have only one target, and can have
only one WITH expressions. This value is tested for a match in a manner similar
to the CASE statement.
with
withEXPRESSION
EXPRESSIONselect
select
TARGET
TARGET<=
<={EXPRESSION
{EXPRESSIONwhen
whenCHOICES,};
CHOICES,};
Example
with
withSIGNAL
SIGNALselect
select
ZZ<=
AAwhen
<=
when15,
15,
BBwhen
when22,
22,
CCwhen
whenOTHERS;
OTHERS;
Note: You cannot use Selected signal assignment in a process.
EE 595 EDA / ASIC Design Lab
Selected Signal Assignment
Example
entity
entityEXAMPLE
EXAMPLEisis
port
port(A,B,
(A,B,C,
C,SEL
SEL
ZZ
: :inininteger
integerrange
range00toto7;7;
: :out
outinteger
integerrange
range00toto7);
7);
end
endEXAMPLE;
EXAMPLE;
architecture
architectureCASE_TYPE
CASE_TYPEofofEXAMPLE
EXAMPLEisis
begin
begin
process
process(A,
(A,B,B,C,
C,SEL)
SEL)
begin
begin
case
case SEL
SELisis
architecture
architectureSEL_TYPE
SEL_TYPEofofEXAMPLE
EXAMPLEisis
when
when00toto44=>
=>
begin
begin
ZZ<=
<=B;B;
with
withSEL
SELselect
select
when
when55=>
=>
ZZ<=
BB when
<=
when00toto4,4,
ZZ<=
C;
<= C;
CC when
when5,5,
when
whenOTHERS
OTHERS=>
=>
AA when
whenOTHERS;
OTHERS;
ZZ<=
<=A;A;
end
SEL_TYPE.
end SEL_TYPE.
end
endcase;
case;
end
endprocess;
process;
end
IF_TYPE;
end IF_TYPE;
EE 595 EDA / ASIC Design Lab
Concurrent Procedure Call
„
„
„
„
IN, OUT and INOUT parameter modes
Allows return of more than 1 value (unlike function
call)
Considered a statement
Equivalent to a process containing the single
procedure call followed by a wait on parameters of
mode in or inout.
EE 595 EDA / ASIC Design Lab
Concurrent Procedure Call
Example
architecture
architecture......
begin
begin
VECTOR_TO_INT(BITSTUFF,
VECTOR_TO_INT(BITSTUFF,FLAG,
FLAG,NUMBER);
NUMBER);
end;
end;
architecture
architecture......
begin
begin
process
process
begin
begin
VECTOR_TO_INT(BITSTUFF,
VECTOR_TO_INT(BITSTUFF,FLAG,
FLAG,NUMBER);
NUMBER);
wait
waiton
onBITSTUFF,
BITSTUFF,NUMBER;
NUMBER;
end
endprocess;
process;
end;
end;
NUMBER was inout, procedure changed NUMBER so procedure run again
EE 595 EDA / ASIC Design Lab
Sequential vs. Concurrent
Statement in Simulation Cycle
„
VHDL is inherently a concurrent language
„
„
„
„
All VHDL processes execute concurrently
Concurrent signal assignment statements are actually oneline processes
VHDL statements execute sequentially within a
process
Concurrent processes with sequential execution
within a process offers maximum flexibility
„
„
Supports various levels of abstraction
Supports modeling of concurrent and sequential events as
observed in real systems
EE 595 EDA / ASIC Design Lab
Blocks
„
Blocks are concurrent statements and provide
a mechanism to partition an architecture
description
„
Items declared in declarative region of block are
visible only inside the block, e.g. :
„
„
„
signals, subprograms
Blocks may be nested to define a hierarchical
partitioning of the architectural description
Blocks may contain Guards for disabling
drives.
EE 595 EDA / ASIC Design Lab
Blocks
[LABEL:]
[LABEL:]block
block[(BOOLEAN
[(BOOLEANEXPRESSION)]
EXPRESSION)]
{DECLARATIONS}
{DECLARATIONS}
begin
begin
.....
----Concurrent
.....
ConcurrentStatements
Statements
end
endblock;
block;
Declarations declare objects local to the block and can be any of following:
„
„
„
„
USE clause
Subprogram declaration and body
Type, constants, signal declarations
Component declaration
EE 595 EDA / ASIC Design Lab
Blocks
Must have
a label
May have
a label
„
„
„
B2:
B2:block
block
begin
begin
C1
C1::EE<=
<=CC++D;
D;
C2
C2::CC<=
<= AA++B;
B;
end
end block;
block;
Blocks can be nested
Objects declared in a BLOCK are visible to that block and all blocks nested
within.
When a child block inside a parent block declares an object with the same name
as one in the parent block, the child’s declaration overrides that of the parent.
EE 595 EDA / ASIC Design Lab
Nested Blocks
B1:
B1:block
block
signal
signalS:
S:Bit;
Bit;
begin
begin
SS<=
<=AAand
andB;
B;
B2:
block
B2: block
signal
signalS:
S:Bit;
Bit;
begin
begin
SS<=
<=CCand
andD;
D;
B3:
B3:block
block
begin
begin
ZZ<=
<=S;
S;
end
endblock;
block;
end
endblock;
block;
YY<=
<=S;
S;
end
endblock;
block;
EE 595 EDA / ASIC Design Lab
--------Declaring
Declaringfirst
firstSSininblock
blockB1
B1
--------using
usingSSininB1
B1
--------Declaring
Declaringsecond
secondSSininblock
blockB2
B2
--------using
usingSSininB2
B2
--------still
stillusing
usingSSininB2
B2
--------B3
B3 ------(Z
--(Z<=
<=CCand
andD)
D)
--------B2
B2
--------using
usingSSfrom
fromB1
B1
--------B1
--------(Y
B1
(Y<=
<=AAand
andB)
B)
Guarded Blocks
„
Can be for modeling latches, clocked logic, bus controllers
„
The Guard is a boolean expression
„
„
„
„
Signal named “GUARD” is implicitly created in block and may be
referenced
Signal assignment statements with signal kind of BUS or REGISTER
can use Guard as enable.
When Guard is true, normal signal assignment activity may
occur
When Guard is false, drivers may be disconnected
EE 595 EDA / ASIC Design Lab
Guard Expression
„
A block can have a Boolean “Guard expression”
B2:
B2:block
block(SELECT
(SELECT==‘1’)
‘1’)
begin
begin
ZZ<=
<=IN_1
IN_1when
whenGUARD
GUARDelse
elseIN_0;
IN_0;
end
endblock;
block;
„
„
„
„
Equivalent to GUARD <= (SELECT = ‘1’); (sensitive to SELECT)
The Boolean signal GUARD is created automatically when block
has a “guard expression”
As shown in the above example, you can test the signal GUARD
Guarded Signal assignment are built-in to the
language/simulator
EE 595 EDA / ASIC Design Lab
Guarded Signal Assignments
„
execute when block guard expression is true
architecture
architectureREG
REGof
ofLATCH
LATCHisis
signal
signalQ:
Q:Std_Logic
Std_Logicregister
register:=
:=‘U’;
‘U’;
begin
begin
B2:
B2:block
block(ENABLE
(ENABLE==‘1’)
‘1’)
begin
begin
QQ<=
<=guarded
guardedD;
D;
end
endblock;
block;
„
The signal assignment to Q only occurs when
GUARD is true
EE 595 EDA / ASIC Design Lab
Guarded Signal Kinds
„
guarded signals are of a signal kind; bus I register.
signal
signalQ:
Q:Std_Logic
Std_Logicregister
register:=:=‘U’;
‘U’;
begin
begin
B2:
B2:block
block(ENABLE
(ENABLE==‘1’)
‘1’)
begin
begin
QQ<=
<=guarded
guardedD;
D;
end
endblock;
block;
„
„
„
Q may be declared as kind register or bus
Q must be of a resolved type (none of the types in
Std.standard are resolved.)
Signal kind register or bus can be disconnected.
EE 595 EDA / ASIC Design Lab
Disconnects
„
„
„
„
When the Guard expression is false, signals assigned with
guarded assignments are said to be disconnected.
Signals of kind Register retain their value when disconnected.
Signals of kind Bus change to their default value when
disconnected. (the default value of std_logic is ‘U’)
Signals of kind bus and register can only be assigned with a
guarded signal assignment.
EE 595 EDA / ASIC Design Lab
Drivers
„
Drivers are created by signal assignment statements.
„
Drivers contain present and future values.
„
A driver is a contributor to a signal value.
„
Value of a signal is the resolution of all of the driver values
„
Multiple assignments in parallel may be error prone.
EE 595 EDA / ASIC Design Lab
Resolution Function
„
No Resolution Functions are built into VHDL
„
Vendor or User provided Functions
„
Resolution Functions are called automatically
„
Multiple Driver-values are passed in through
parameters.
EE 595 EDA / ASIC Design Lab
Resolution Function
„„
„„
„„
„„
„„
„„
„„
Resolves
Resolvesvalue
valueof
ofsignal
signalwith
withmultiple
multipledrivers
drivers
Required
Requiredwhen
whensignal
signalhas
hasmultiple
multipledrivers
drivers
Function
Functioncalled
calledafter
afterany
anyassignment
assignmentto
tosignal
signal
Passed
Passedaavariable
variablelength
lengtharray
arrayof
ofsignal
signalvalues
valuesto
tobe
be
resolved
resolved
User
Userdefinable:
definable:typically
typicallywired
wiredand,
and,or
or3-state
3-state
Associates
Associatesthe
theresolution
resolutionfunction
functionwith
withsubtype
subtype
(which
(whichbecomes
becomesaaresolved
resolvedtype)
type)
EE 595 EDA / ASIC Design Lab
Three State Bus
+5v
‘H’
‘H’ ‘Z’
‘Z’ ‘0’
‘z’
‘z’
resolution
‘0’
function
EE 595 EDA / ASIC Design Lab
‘0’
‘0’
Driver Resolution
Initial Value
Driver Values
Z
Z
Z
H
EE 595 EDA / ASIC Design Lab
H
Driver Resolution Conflict
Initial Value
Driver Values
Z
1
Z
1
1
X
EE 595 EDA / ASIC Design Lab
0
Bus Resolution Function
Example
package
packageFOURPACK
FOURPACKisis
type
typeFOURVAL
FOURVALisis(X,
(X,L,L,H,
H,Z);
Z);
type
typeFOURVAL_VECTOR
FOURVAL_VECTORisisarray(natural
array(naturalrange
range<>)
<>)of
ofFOURVAL;
FOURVAL;
function
functionRESOLVE
RESOLVE(S:
(S:FOURVAL_VECTOR)
FOURVAL_VECTOR)return
returnFOURVAL;
FOURVAL;
end
endFOURPACK;
FOURPACK;
package
packagebody
bodyFOURPACK
FOURPACKisis
function
functionRESOLVE
RESOLVE(S:
(S:FOURVAL_VECTOR)
FOURVAL_VECTOR)return
returnisis
variable
variableRESOLVE
RESOLVE(S:
(S:FOURVAL_VECTOR)
FOURVAL_VECTOR)return
returnFOURVAL
FOURVALisis
begin
begin
for
forI Iin
inS’RANGE
S’RANGEloop
loop
case
caseRESULT
RESULTisis
EE 595 EDA / ASIC Design Lab
Bus Resolution Function
Example (cont’d)
when
whenZZ=>
=>
case
caseS(i)
S(i)isis
when
whenHH=>
=>
RESULT
RESULT:=:=H;H;
when
whenLL=>
=>
RESULT
RESULT:=:=L;L;
when
whenXX=>
=>
RESULT
RESULT:=:=X;X;
when
whenOTHERS
OTHERS=>
=>
null;
null;
end
endcase;
case;
when
whenLL=>
=>
case
caseS(i)
S(i)isis
when
whenHH=>
=>
RESULT
RESULT:=:=X;X;
when
whenXX=>
=> RESULT := X;
RESULT := X;
when
OTHERS
when OTHERS=>
=>
NULL;
NULL;
EE 595 EDA / ASIC Design Lab
;;
::
Bus Resolution Function
Example (cont’d)
end
endcase;
case;
when
whenHH=>
=>
case
caseS(i)
S(i)isis
when
whenLL=>
=>
RESULT
RESULT:=:=X;
X;
when
whenXX=>
=>
RESULT
RESULT:=:=X;
X;
when
OTHERS
when OTHERS=>
=>
end
case;
end case;
when
whenXX=>
=>
RESULT
:=
X;
RESULT := X;
end
endcase;
case;
end
loop;
end loop;
return
returnRESULT;
RESULT;
end
RESOLVE;
end RESOLVE;
end
FOURPACK;
end FOURPACK;
EE 595 EDA / ASIC Design Lab
Resolution Function for
Subtype
package
packageFOURPACK
FOURPACKisis
type
typeFOURVAL
FOURVALisis(X,
(X,L,L,H,
H,Z);
Z);
type
FOUR_VECTOR
is
array
type FOUR_VECTOR is array(Natural
(Naturalrange
range<>)
<>)
of
FOURVAL;
of FOURVAL;
function
functionRESOLVE
RESOLVE(S:
(S:FOURVAL_VECTOR)
FOURVAL_VECTOR)return
returnFOURVAL;
FOURVAL;
subtype
subtypeRESFOUR
RESFOURisisRESOLVE
RESOLVEFOURVAL,
FOURVAL,
end
endFOURPACK;
FOURPACK;
use
useWork.FOURPACK.all;
Work.FOURPACK.all;
entity
entity......
architecture
architecture......
signal
signalA,
A,BB: :RESFOUR;.
RESFOUR;.
EE 595 EDA / ASIC Design Lab
Summary
„
Signals with Multiple Drivers require Resolution
„
Resolution Functions are associated with subtype
„
The resolved type and declaration and resolution
function are usually declared in a Package
EE 595 EDA / ASIC Design Lab
Predefined Attributes
„
„
„
Data obtained from Blocks, Signals, Types and Subtypes
Return values such as:
„ length of an array type
„ time since last signal change
„ range of values in a type
Predefined attributes are useful for performing certain type of
functions such as:
„ timing checks
„ bounds
„ clock edge detection
„ type conversion
EE 595 EDA / ASIC Design Lab
Array Type Bound Example
process (...)
type BIT_RANGE is array (31 DOWNTO 0) of Bit;
variable LEFT_RANGE, RIGHT_RANGE,
HIGH_RANGE, LOW_RANGE: integer;
begin
LEFT_RANGE := BIT_RANGE’left;
-- returns 31
RIGHT_RANGE := BIT_RANGE’right;
-- returns 0
HIGH_RANGE := BIT_RANGE’high
-- returns 31
LOW_RANGE := BIT_RANGE’low;
-- returns 0
end process;
EE 595 EDA / ASIC Design Lab
Array Bound
Example
type
typeT_RAM_DATA
T_RAM_DATAis
isarray
array(0
(0TO
TO511)
511)of
ofinteger;
integer;
variable
variableRAM_DATA
RAM_DATA: :T_RAM_DATA;
T_RAM_DATA;
..
..
for
fori iin
inRAM_DATA’low
RAM_DATA’lowTO
TORAM_DATA’high
RAM_DATA’highloop
loop
RAM_DATA(i)
RAM_DATA(i):=
:=0;
0;
end
endloop;
loop;
EE 595 EDA / ASIC Design Lab
Multi-Range Array Attributes
„
„
„
„
‘left(N) -returns left bound of index range N
‘right(N) -returns right bound of index range N
‘high(N) -returns upper bound of index range N
‘low(N) - returns lower bound of index range N
Example
N= 1
2
variable:
variable:MEMORY
MEMORY(0
(0to
to5,
5,00to
to7)
7)of
ofMEM_DATA;
MEM_DATA;
MEMORY
MEMORY‘right(2);
‘right(2);
EE 595 EDA / ASIC Design Lab
Array Length Attributes
„
‘length return of an array or array type
process
process(...)
(...)
type
typeBIT4
BIT4is
isarray
array(0
(0TO
TO3)
3)of
ofBit;
Bit;
type
typeBIT_STRANGE
BIT_STRANGEis
isarray(10
array(10TO
TO20)
20)of
ofBit;
Bit;
variable
variableLEN1,
LEN1,LEN2:
LEN2:integer;
integer;
begin
begin
LEN1
----return
LEN1:=
:=BIT4’length;
BIT4’length;
return44
LEN2
----returns
LEN2:=
:=BIT_STRANGE’length;
BIT_STRANGE’length;
returns11
11
end
endprocess;
process;
EE 595 EDA / ASIC Design Lab
Range Attributes
NAME ‘range - returns the declared range of a particular type
NAME’reverse_range - returns the declared range of a particular type in
reverse order
Example:
Example:
function
functionVECTOR_TO_INT(STUFF:
VECTOR_TO_INT(STUFF:Bit_Vector)
Bit_Vector)return
returninteger
integeris
is
variable
variableRESULT:
RESULT:Integer
Integer:=
:=0;
0;
begin
begin
for
fori iin
inSTUFF
STUFF‘range
‘rangeloop
loop
....
....
EE 595 EDA / ASIC Design Lab
Type Attributes Position
Function
TYPENAME ‘succ(V) - returns next value in type after input value
TYPENAME ’pred(V) - returns previous value in type before input value
TYPENAME ‘leftof(V) - returns value immediately to left of input value
TYPENAME ‘rightof(V) - returns value immediately to right of input value
TYPENAME ‘pos(V) - returns type position number from type value
TYPENAME ‘val(P) - returns type value from type position number
‘base - returns base type of type or subtype
EE 595 EDA / ASIC Design Lab
Attributes Exercise
type
typeCOLOR
COLORisis(RED,
(RED,BLUE,
BLUE,GREEN,
GREEN,YELLOW,
YELLOW,BLACK);
BLACK);
subtype
subtypeCOLOR_GUN
COLOR_GUNisisCOLOR
COLORrange
rangeRED
REDto
toGREEN;
GREEN;
variable
variableA:
A:COLOR;
COLOR;
begin
begin
A:=
A:=COLOR‘low;
COLOR‘low;
A:=
A:=COLOR
COLOR‘succ(RED);
‘succ(RED);
A:=
A:=COLOR_GUN’base’right;
COLOR_GUN’base’right;
A:=
A:=COLOR’base’left;
COLOR’base’left;
A:=
A:=COLOR_GUN’base’succ(GREEN);
COLOR_GUN’base’succ(GREEN);
EE 595 EDA / ASIC Design Lab
Attribute
Example
type
typeCURRENT
CURRENTisisrange
range00TO
TO1000000
1000000
units
uA:
units uA:
mA
mA==1000
1000uA;
uA;
AA==1000
1000mA;
mA;
end
units;
end units;
type
typeVOLTAGE
VOLTAGEisisrange
range00TO
TO1000000
1000000
units
uv
units uv
mV
mV==1000
1000uV;
uV;
VV==1000
1000mV;
mV;
end
units;
end units;
type
typeRESISTENCE
RESISTENCEisisrange
range00TO
TO1000000
1000000
units
Ohm;
units Ohm;
KOhm
KOhm==1000
1000Ohm;
Ohm;
end
endunits;
units;
EE 595 EDA / ASIC Design Lab
;;
Attribute
Example (cont’d)
entity
entityCALC_RES
CALC_RESisis
port
port(I(I: :in
inCURRENT;
CURRENT;EE: :in
inVOLTAGE;
VOLTAGE;
RR: :out
outRESISTANCE);
RESISTANCE);
end
endCALC_RES;
CALC_RES;
architecture
architectureBEHAVE
BEHAVEof
ofCALC_RES
CALC_RESisis
begin
begin
process
process(I,E)
(I,E)begin
begin
RR<=
<=RESISTANCE’val(VOLTAGE’pos(I)/CURRENT’pos(E));
RESISTANCE’val(VOLTAGE’pos(I)/CURRENT’pos(E));
end
endprocess;
process;
end
endBEHAVE;
BEHAVE;
EE 595 EDA / ASIC Design Lab
Signal Attributes
„
„
„
„
„
SIGNAL’event - returns True if an event occurred on this signal
during this delta
SIGNAL’active - returns True if a transaction occurred this delta
SIGNAL’last_event - returns the elapsed time since previous
event
SIGNAL’last_value - returns previous value of signal before last
event
SIGNAL’last_active - returns time elapsed since previous
transaction
EE 595 EDA / ASIC Design Lab
Signal Attribute
Example
library
libraryIEEE;
IEEE;use
useIEEE.std_logic_1164.all;
IEEE.std_logic_1164.all;
entity
entityDFLOP
DFLOPisis
port
port(D,
(D,CLK
CLK: :ininstd_logic;
std_logic;QQ: :out
outstd_logic);
std_logic);
end
endDFLOP;
DFLOP;
architecture
architectureDFF
DFFof
ofDFLOP
DFLOPisis
begin
begin
process
process(CLK)
(CLK)
begin
begin
ifif(CLK
(CLK==‘1’)
‘1’)and
and(CLK’event)
(CLK’event)and
and(CLK’last_value
(CLK’last_value==‘0’)
‘0’)then
then
QQ<=
D;
<= D;
end
if;
end if;
end
process;
end process;
end
DFF;
end DFF;
EE 595 EDA / ASIC Design Lab
Derived Signal Attribute
SIGNAL’delayed [(time)] - creates a signal that follows
reference signal, delayed by time value
SIGNAL’stable[(time)] - creates a signal that is True when the
reference signal has no events for time value.
SIGNAL’quiet[(time)] - creates a signal that is True when the
reference signal has no transactions for time value
SIGNAL ‘transaction - creates a signal of type Bit that toggles
(has a transition) for every transaction on reference signal
EE 595 EDA / ASIC Design Lab
Stable Attribute
Example
architecture BEHAVE of PULSE_GEN is
begin
B <= A’stable(10 ns);
end PULSE_GEN;
A
B
0
10
20
EE 595 EDA / ASIC Design Lab
30
40
50
60
70
80
90
User Defined Attributes
„
Attach data to objects
„
Data type user defined
„
Data is constant
„
Accessed with same syntax as predefined attributes
EE 595 EDA / ASIC Design Lab
User Defined Attributes
Example
package
packageBOARD_ATTRS
BOARD_ATTRSis
is
type
typePACKAGE_TYPES
PACKAGE_TYPESisis
(LEADLESS,
(LEADLESS,PGA,
PGA,DIP);
DIP);
attribute
attributePACKAGE_TYPE
PACKAGE_TYPE: :
PACKAGE_TYPES;
PACKAGE_TYPES;
attribute
attributePACKAGE_LOC
PACKAGE_LOC: :Integer;
Integer;
end
endBOARD_ATTRS;
BOARD_ATTRS;
use
useWork.BOARD_ATTRS.all;
Work.BOARD_ATTRS.all;
entity
entityBOARD
BOARDis
isport(...);
port(...);end
endBOARD;
BOARD;
architecture
architectureCPU_BOARD
CPU_BOARDof
ofBOARD
BOARDisis
EE 595 EDA / ASIC Design Lab
User Defined Attributes
Example (cont’d)
component
componentMC68040
MC68040
generic
generic(.......);
(.......);port
port(........);
(........);
end
endcomponent;
component;
signal
signalA:
A:integer,
integer,B:
B:PACKAGE_TYPE;
PACKAGE_TYPE;
attribute
attributePACKAGE_TYPE
PACKAGE_TYPEof
ofMC68040
MC68040: :component
componentis
isPGA
PGA
attribute
attributePACKAGE_LOC
PACKAGE_LOCof
ofMC68040
MC68040: :component
componentis
is20;
20;
begin
begin
AA<=
----returns
<=MC68040’PACKAGE_LOC;
MC68040’PACKAGE_LOC;
returns20
20
BB<=
<=MC68040’PACKAGE_TYPE
MC68040’PACKAGE_TYPE ----returns
returnsPGA
PGA
end
endCPU_BOARD;
CPU_BOARD;
EE 595 EDA / ASIC Design Lab
Recall: Three-State Logic
Type BIT3
‘0’
‘1’
‘Z’
architecture
architecture …
…
begin
begin
C<=
C<=A;
A;
C<=B
C<=B
...
...
How does a simulator resolve the logic values?
EE 595 EDA / ASIC Design Lab
Three- State Multiple Drivers
Example
architecture BEHAVE of STATE3 is
signal S, SIG_A, SIG_B : BIT3;
begin
A: process (SIG_A, ASEL)
begin
S <= ‘Z’;
if (ASEL) then
S <= SIG_A;
end if;
end process;
B: process (SIG_B, BSEL)
begin
S <= ‘Z’;
if (BSEL) then
S <= SIG_B;
end if;
end process;
end BEHAVE;
EE 595 EDA / ASIC Design Lab
ASEL
SIG_A
BSEL
SIG_B
Resolution Required
Requires a resolution function for type BIT3
S
State Machines
To design a state machine in VHDL, each state can be translated to a
case-when construct. The state transitions can then be specified in
if-then-else statements.
For, example, to translate the state flow diagram into VHDL, we begin
by defining an enumeration type, consisting of the state names, and
declaring two signals of that type:
type
typeSTATETYPE
STATETYPEis
is(IDLE,
(IDLE,DECISION,
DECISION,READ,
READ,WRITE);
WRITE);
signal
signalPRESENT_STATE,
PRESENT_STATE,NEXT_STATE
NEXT_STATE::STATETYPE;
STATETYPE;
EE 595 EDA / ASIC Design Lab
State Machines (cont’d)
Next, we create a process. Next_state is determined by a function of the
present_state and the inputs (read and read_write.)
STATE_COMB:
STATE_COMB:process
process(PRESENT_STATE,
(PRESENT_STATE,READ_WRITE,
READ_WRITE,READY)
READY)
begin
begin
......
end
endprocess
processSTATE_COMB;
STATE_COMB;
Within the process we describe the state machine transitions.
We open a case-when statement and specify the first case
(when condition), which is for the idle state. For this case, we
specify the outputs defined by the idle state and transitions
from it :
EE 595 EDA / ASIC Design Lab
State Machines (cont’d)
STATE_COMB: process (PRESENT_STATE, READ_WRITE, READY)
begin
case PRESENT_STATE is
WHEN idle =>
OE <= ‘0’; WE <= ‘0’;
if READY = ‘1’ then
NEXT_STATE <= DECISION;
else
-- else not necessary
NEXT_STATE => IDLE; -- included for readability
end if;
The above process indicates what the next_state assignment will be based
on present-state and present inputs, but it does not indicate when the next
state becomes the present state .This happens synchronously, on the
rising edge of a clock.
EE 595 EDA / ASIC Design Lab
Two-Process FSM
Example
ready
idle
ready
ready
ready
decision
read_write
read_write
write
read
ready
ready
State
Outputs
OE WE
Idle
decision
write
read
0
0
0
1
0
0
1
0
entity EXAMPLE is
entity EXAMPLE is
port( READ_WRITE, READY, CLK
port( READ_WRITE, READY, CLK
OE, WE
OE, WE
end example;
end example;
: in Bit;
: in Bit;
: out Bit);
: out Bit);
architecture STATE_MACHINE of EXAMPLE is
architecture STATE_MACHINE of EXAMPLE is
type STATETYPE is (IDLE, DECISION, READ, WRITE);
type STATETYPE is (IDLE, DECISION, READ, WRITE);
signal PRESENT_STATE, NEXT_STATE : STATETYPE;
signal PRESENT_STATE, NEXT_STATE : STATETYPE;
begin
begin
STATE_COMB: PROCESS(PRESENT_STATE, READ_WRITE, READY)
STATE_COMB: PROCESS(PRESENT_STATE, READ_WRITE, READY)
case PRESENT_STATE is
case PRESENT_STATE is
when IDLE =>
OE <= ‘0’; WE <= ‘0’;
when IDLE =>
OE <= ‘0’; WE <= ‘0’;
if READY = ‘1’ then
if READY = ‘1’ then
NEXT_STATE <= DECISION;
NEXT_STATE <= DECISION;
else
else
NEXT_STATE <= IDLE;
NEXT_STATE <= IDLE;
end if;
end if;
when DECISION => OE <= ‘0’; WE <= ‘0’;
when DECISION => OE <= ‘0’; WE <= ‘0’;
if (READ_WRITE = ‘1’) then
if (READ_WRITE = ‘1’) then
NEXT_STATE <= READ;
NEXT_STATE <= READ;
else
else
NEXT_STATE <= WRITE;
NEXT_STATE <= WRITE;
end if;
end if;
EE 595 EDA / ASIC Design Lab
Example- Two- Process FSM
when
OE
when READ
READ =>
=>
OE <=
<= ‘1’;
‘1’; WE
WE <=
<= ‘0’;
‘0’;
(if
READY
=
‘1’
)
then
(if READY = ‘1’ ) then
NEXT_STATE
NEXT_STATE <=
<= IDLE;
IDLE;
else
else
NEXT_STATE
NEXT_STATE <=
<= READ;
READ;
end
if;
end if;
when
whenWRITE
WRITE =>
=> OE
OE <=
<= ‘0’;
‘0’; WE
WE <=
<= ‘1’;
‘1’;
ifif (READY
=
‘1’)
then
(READY = ‘1’) then
NEXT_STATE
NEXT_STATE <=
<= IDLE;
IDLE;
else
else
NEXT_STATE
NEXT_STATE <=
<= WRITE;
WRITE;
end
if;
end if;
end
case;
end case;
end
end process
processSTATE_COMB;
STATE_COMB;
EE 595 EDA / ASIC Design Lab
Two- Process FSM
Example
STATE_CLOCKED
STATE_CLOCKED: :process(CLK)
process(CLK)
begin
begin
ifif(CLK’EVENT
(CLK’EVENTAND
ANDCLK
CLK==‘1’
‘1’))then
then
PRESENT_STATE
PRESENT_STATE <=
<= NEXT_STATE;
NEXT_STATE;
end
endif;
if;
end
endprocess
processSTATE_CLOCKED;
STATE_CLOCKED;
end
endarchitecture
architectureSTATE_MACHINE;
STATE_MACHINE;
----“architecture
“architecture““isisoptional;
optional;for
forclarity.
clarity.
EE 595 EDA / ASIC Design Lab
Combinational/Sequential
VHDL Examples
EE 595 EDA / ASIC Design Lab
VHDL MUX
process
process(SELECT,
(SELECT,A,
A,B)
B)
begin
begin
case
caseSELECT
SELECTisis
when
when‘0’
‘0’=>
=>DATAOUT
DATAOUT<=
<=A;
A;
when
‘1’
=>
DATAOUT
<=
B;
when ‘1’ => DATAOUT <= B;
when
whenothers
others=>
=>null;
null;
end
case;
end case;
----no
nopriority
prioritygiven
givenbut
but
----using
if
loop
we
using if loop we
----can
canprioritize
prioritize
A
end
endprocess;
process;
DATAOUT
B
SELECT
EE 595 EDA / ASIC Design Lab
Combinational Logic
a
b
c
d
Combinational Logic
Comb_logic
y
Models representing a combinational block described by the truth table
are given below:
AB
CD
“00”
“01”
“11”
“10”
“00”
‘0’
‘1’
‘1’
‘0’
“01”
‘1’
‘1’
‘1’
‘0’
“11”
‘0’
‘1’
‘1’
‘1’
“10”
‘0’
‘0’
‘0’
‘0’
EE 595 EDA / ASIC Design Lab
y = C’b+db+cda+c’da’
Combinational Logic
entity
entityCOMB_LOGIC
COMB_LOGICisis ----yy==c’d+db+cda+c’da’
c’d+db+cda+c’da’
generic
(P_DELAY
:
time);
generic (P_DELAY : time);
port
port(A,
(A,B,B,C,
C,DD: :ininBit;
Bit;
YY: :out
outBit);
Bit);
end
----behavior
endCOMB_LOGIC;
COMB_LOGIC;
behaviorfrom
fromthe
thetruth
truthtable
table
----process
processstatement
statementand
andsequential
sequentialstatements
statements
architecture
ARCH2
of
COMB_LOGIC
is
architecture ARCH2 of COMB_LOGIC is
begin
begin
process
process(A,
(A,B,B,C,
C,D)
D)
variable
TEMP
variable TEMP: :Bit_Vector
Bit_Vector(3(3DOWNTO
DOWNTO0);
0);
begin
begin
TEMP
TEMP:=:=A&B&C&D;
A&B&C&D;
case
caseTEMP
TEMPisis
when
whenb”0000”
b”0000”| |b”1000”
b”1000”| |b”1001
b”1001| |b”0011”
b”0011”| |
b”0010”
|
b”0110”
|
b”1110”
|
b”1010”
b”0010” | b”0110” | b”1110” | b”1010” =>
=>
yy<=
<=‘0’;
‘0’;
when
whenOTHERS
OTHERS=>
=> yy<=
<=‘1’;
‘1’;
end
endcase;
case;
end
endprocess;
process;
end
ARCH2;
end ARCH2;
EE 595 EDA / ASIC Design Lab
Combinational Logic
-----
y = c’b+db+cda+c’da’
entity
entityCOMB_LOGIC
COMB_LOGICisis
generic
generic(P_DELAY
(P_DELAY: :TIME);
TIME);
port
port(A,
(A,B,
B,C,
C,D:
D:in
inBit;
Bit;
YY: :out
Bit);
out Bit);
end
COMB_LOGIC;
end COMB_LOGIC;
----simple
simplesignal
signalassignment
assignmentstatement,
statement,RTL
RTL
architecture
architectureARCH1
ARCH1of
ofCOMB_LOGIC
COMB_LOGICisis
begin
begin
YY<=
<=((NOT
((NOTC)
C)AND
ANDB)
B)OR
OR(D
(DAND
ANDB)
B)OR
OR
(C
AND
D
AND
A)
OR
((NOT
C)
AND
D
(C AND D AND A) OR ((NOT C) AND DAND
AND(NOT
(NOTA));
A));
end
ARCH1;
end ARCH1;
EE 595 EDA / ASIC Design Lab
VHDL Latch
process (DATAIN, ENABLE)
begin
if ENABLE = ‘1’
DATAOUT <= DATAIN;
-- it does not explicitly
-- defines other
-- conditional values
end if;
end process;
datain
d
enable
en
EE 595 EDA / ASIC Design Lab
q
dataout
VHDL Tri-State Bus
process
process(DATA1,
(DATA1,ENABLE1)
ENABLE1)
begin
begin
ififENABLE
ENABLE==‘0’‘0’then
then
DATA
DATA<=
<=DATA1;
DATA1;
else
else
DATAOUT
DATAOUT<=
<=“ZZ”;
“ZZ”;
end
endif;if;
end
endprocess;
process;
----drive
driveDATAOUT
DATAOUT
data(0)
enable1
dataout(0)
data2(0)
enable2
EE 595 EDA / ASIC Design Lab
VHDL Tri-State Bus(cont)
process
process(DATA2,
(DATA2,ENABLE2)
ENABLE2)
begin
begin
ififENABLE
ENABLE==‘0’‘0’then
then
DATAOUT
DATAOUT<=
<=DATA2
DATA2
else
else
DATAOUT
DATAOUT<=
<=“ZZ”;
“ZZ”;
end
if;
end if;
end
endprocess;
process;
----also
alsodrive’s
drive’s
data(1)
enable1
data(2)
enable2
EE 595 EDA / ASIC Design Lab
dataout(1)
VHDL Register
asynchronous reset
data(0)
dataout(0)
clk
reset
datain(1)
dataout(1)
datain(2)
dataout(2)
datain(3)
dataout(3)
EE 595 EDA / ASIC Design Lab
VHDL Register
process
process(RESET,
(RESET,CLK)
CLK)
begin
begin
ififRESET
RESET==‘0’
‘0’then
then
DATAOUT
DATAOUT<=
<=“0000”;
“0000”;
elsif
elsif CLK’event
CLK’eventand
andCLK
CLK==‘1’
‘1’then
then----rising
risingedge
edge
DATAOUT
DATAOUT<=
<=DATAIN;
DATAIN; ----of
ofclock
clock
end
endif;
if;
end
endprocess;
process;
Asynchronous reset does not depend on clock.
EE 595 EDA / ASIC Design Lab
Interface Description of 74LS161
4-bit Synchronous Counter
clock
load
ripple_out
clear
enable_p
enable_t
4
data
EE 595 EDA / ASIC Design Lab
q
4
Interface Description of 74LS161
4-bit Synchronous Counter
Function Table of 74LS161 4 - bit synchronous counter
Clock
load
clear
enable_p
enable_t
Operation
X
X
low
X
X
asynchronous clear
rising
low
high
X
X
load input data
rising
high
high
high
high
increment court
* X means Don’t Care
* ripple_out = 1 when count = decimal 15 and enable_t = ‘1’
EE 595 EDA / ASIC Design Lab