Architekturen und Einsatz von FPGAs
mit integrierten Prozessor Kernen
Hans-Joachim Gelke
Institute of Embedded Systems
Professur für Mikroelektronik
Zürcher Fachhochschule
Contents
• Überblick: Aufbau moderner FPGA
• Einblick: Eigenschaften und Architektur von SoC FPGA
• Nachbarblick: Unterschiede zwischen Hauptkonkurrenten
• Ausblick: SoC FPGA der 2ten Generation
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Digital hardware of the past
Program
DRAM & Controller Memory
Communications
Controller
Customer
Specific
Logic
Processor
Scratch SRAM
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Not flexible Hardware
4
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Classic FPGA
FPGA Fabric
Interconnection between
Logic Cells
Logic Cell
Lookup Table
5
Image courtesy of Clieve Maxfield
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FPGA with Hard Silicon Blocks
Logic Element
Block RAM
Multiplier
DSP block
PLL
Clock Manager
I/O Bank
Transceiver
6
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Example of DSP hard block
FIR Filter
Register
Filter coefficient
Source: Altera DSP Users Guide
Accumulator
Digital Signal Processing Slice
Scalable Multiplier Accumulator
Konfig.
Altera
Cyclone
Xilinx
Zync
1
9x9
25x18
2
18x19
35x25
3
27x27
42x18
7
Source: Xilinx Users Guide
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SoC FPGA & Silicon Convergence
Classic
FPGA
General
Processor
ASIC
ASSP
SOC
FPGA
+ Great flexibility
- No Hard Processors
- Licensing costs for IP
+ Customer Specific
+ Good power efficiency
+ Great power efficiency
+ Less board space
- High development costs
+ High interconnect speed
- High turnaround times
- Poor flexibility
+ Software programmable
+ Power efficient
+ Great flexibility
+ No licenses
- Few application specific features
+ Great power efficiency
-Poor flexibility
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Architecture of SoC FPGA
SoC FPGA
MPU Portion
Flash
Controllers
FPGA Portion
SDRAM Controller
Subsystem
Control
Block
User
I/O
HSSI
Transceivers
Cortex-A9 MPU Subsystem
ProcessorFPGA
Bridges
On-Chip
Memories
PLLs
Support
Peripherals
Interface
Peripherals
Debug
FPGA Fabric
(LUTs, RAMs, Multipliers & Routing)
PLLs
Hard
PCIe
Hard Memory
Controllers
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GigEth
USB OTG
Static
Memory
Controller
DMA
Scratch
SRAM
Boot
ROM
ARM Cortex-A9
Neon/FPU
L1 Cache
ARM Cortex-A9
Neon/FPU
L1 Cache
L2 Cache
Multiport
DDR2/3 Controller
Debug and Trace
Processor FPGA Bridges
Block
Memory
Multiport
DDR2/3
Controller1)
FPGA Fabric
PCIe
A/D
Conv.2)
Dedicated DDR Pins
UART
CAN
I2C
SPI
SD/SDIO
GPIO
Timer
Interconnect
Dedicated MPU Pins
SoC FPGA Architecture
DSP
Blocks
Transceivers
1) Only
Altera
2) Only Xilinx
10
FPGA Pins
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Processor to FPGA Bridges
Master
Altera
Slave
Dual ARM Cortex-A9
Dual ARM Cortex-A9
L2 Cache
ACP
64-bit
Multiport
DDR3
Controller
64-bit
64-bit
L3 Interconnect 32-bit
64-bit
AXI
MPU/
FPGA
Bridge
64-bit
AXI
Lightweight
Bridge
FPGA/
MPU
Bridge
128-bit
AXI
128-bit
AXI
288
32-bit
AXI
FPGA Fabric
64-bit
256-bit
AXI
256
64-bit
Master/Slave
Interconnect
Scratch
SRAM
@200MHz ~ 100 Gbps
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64-bit AXI
64-bit
32-bit
AXI
L2 Cache
General Purpose AXI
ACP
Xilinx
Scratch
SRAM
64-bit
64-bit
64-bit
High Performance
Memory Interconnect Ports
32-bit
64 32 32 32 AXI
64
64-bit
Multiport
DDR3
Controller
128
64-bit
AXI
FPGA Fabric
64-bit
AXI
64-bit
AXI
64-bit
AXI
256
@200MHz ~ 90 Gbps
11
SoC Processor Cores
Altera
Xilinx
CPU-Core
Dual ARM Cortex-A9 MPCore Dual ARM Cortex-A9 MPCore
Debug
CoreSight
CoreSight
Neon-SIMD
Neon-SIMD
600 - 800 MHz
667 – 1000 MHz
CPU Clock
frequency1)
L1-Cache
(Data/Instruction) 32 KB/ 32KB parity protected
32 KB/ 32KB parity protected
L2-Cache
Scratch SRAM
512KB no ECC parity protected
256KB parity protected
Boot ROM
1) CPU
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512KB ECC protected
64KB ECC protected
64KB
Clock frequency depends on speed grade
128 KB
12
Comparing Altera and Xilinx Low End
Altera Cyclone V 5CSEA5
Xilinx Zync Z-7020
Package Variantes
3
2
FPGA I/O Pins
66 - 288
125 - 200
FPGA Logik
85k Logikelemente
85k Logikzellen
FPGA Block-RAM
3.9 Mbit
4.3 Mbit
SDRAM Controller
32-bit DDR2/DDR3-800
32-bit DDR2/DDR3-1066
DSP Slices
174 (18x19 config.)
220 (18x25 config.)
DSP Performance
104 GMAC/s
158 GMAC/s
A/D Converters
None
2 x 12 bit MSPS 17 inputs
Static Power/W
0.5
0.2
Total Power/W
2.8
2.3
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Comparing Altera and Xilinx Mid End
Altera Arria V5ASTD3
Xilinx Zync Z-7045
Package Variants
3
3
FPGA I/O Pins
178 - 528
250 - 362
FPGA Logik
350k Logikelemente
350k Logikzellen
FPGA Block-RAM
17.2 Mbit
17.4 Mbit
Serial Transceivers 1)
30 x 6.375 Gbits/s
16 x 10.3 Gbit/s
16 x 12.5 Gbps or
SDRAM Controller
32-bit DDR2/DDR3-1066
32-bit DDR2/DDR3-1333
DSP Slices
1618 (18x19 config.)
900 18x25 (config.)
DSP Performance
1197 GMAC/s
1334 GMAC/s
A/D Converters
none
2 x 12 bit MSPS 17 inputs
Static Power/W
2.9
0.311
Total Power/W
9.9
8.0
1) For
largest package
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2nd Generation SoC FPGA
What has the 2nd Generation to offer?
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Intended Altera 2nd Generation
1. Generation
Altera Arria 5
2. Generation
Largest Altera
(Arria 10)
Process
28nm
20 nm Low Power
Prozessor Clock
800 MHz
1.5 GHz (overdrive)
Logic Elements
504k
1150k
Power Dissipation
1x
0.6x
Max Transceivers speed
10.3125 Gbps
28.05 Gbps
Memory Devices
DDR3 SDRAM 1333Mbps
DDR3 SDRAM 2133Mbps
DDR4 SDRAM 2666 Mbps
Soc SRAM
64KB
256kKB
FPGA-MPU Bridge
Up to 64-bit
Up to 128-bit
Code Encryption
-
Secure Boot
DSP Blocks
27 x 27 Multipliers
54 x 54 Multipliers
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Questions
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