Module: Logic Design Lab
Name: ……………………….........................
University no:……………………..
Group no: ……………
Lab Partner Name:
Mr. Mohamed El-Saied
Experiment 10: Flip-Flops
Objective: To realize and implement
 Set-Reset (SR) latch using NOR gates (active high circuit).
 SR, JK, D, and T Flip-Flops using IC’s and breadboard.
Components Required:
 Mini Digital Training and Digital Electronic Sets.
 IC 7404, IC 7408, IC 7411, IC 7474, IC 7476.
Theory:
Logic circuits for digital systems are either combinational or sequential. The output of combinational circuits
depends only on the current inputs. In contrast, sequential circuit depends not only on the current value of the
input but also upon the internal state of the circuit. Basic building blocks (memory elements) of a sequential
circuit are the flip-flops (FFs). The FFs change their output state depending upon inputs at certain interval of
time synchronized with some clock pulse applied to it. Usually any flip-flop has normal inputs, present state
Q(t) as circuit inputs and two outputs; next state Q(t+1) and its complementary value; Q`. We shall discuss
most widely used latches that are listed below.
1. SR flip-flop:
S
0
0
1
1
Symbol of SR latch
R
0
1
0
1
E
0
1
1
1
1
SR flip-flop with Enable line
00
0
1
1
01
11
x
x
10
1
1
Comment
NC
Reset
Set
undefined
Characteristic Table
Logic diagram of SR FF
NOR Implementation (Active high)
Symbol of Clocked
SR FF
Q(t+1)
Q(t)
0
1
X
S
X
0
0
1
1
R
Q(t+1)
Comment
X
Q(t)
NC
0
Q(t)
NC
1
0
Reset
0
1
Set
1
X
undefined
Characteristic Table
Q(t+1)=S+R`Q(t)
1
Edge triggered flip-flop:
The edge-triggered FF means: on the rising or falling edge of the clock, the output Q(t+1) is computed given
the value of the inputs (S and R) at that moment and the previous output Q(t). The output can be only changed
at the clock edge, and if the input changes at other times, the output will be unaffected.
Timing diagram of clocked SR flip-flop
2. JK flip-flop:
The JK flip-flop is the modified version of SR flip-flop with no invalid state; i.e. the state J=K=1 is not
forbidden. It works such that J serves as set input and K serves as reset. The only difference is that for the
combination J=K=1 this flip-flop; now performs an action: it inverts its state.
R=KQ(t)
S=JQ`(t)
Q(t+1)=S+R`Q(t)
= JQ`(t)+(KQ(t))`Q(t)
= JQ`(t)+K`Q(t)
Characteristic equation
Logic diagram of JK FF from SR FF
Symbol of JK FF
CLK
J
0
1
1
1
1
X
0
0
1
1
K
Q(t+1)
comment
X
Q(t)
NC
0
Q(t)
NC
1
0
Reset
0
1
Set
1
Q`(t)
Toggle
Characteristic Table
Pin diagram of IC 7476
2
3. D flip-flop:
R=D`
S=D
Q(t+1)=S+R`Q(t)
= D+D``Q(t)
= D(1+Q(t))
=D
Characteristic equation
Logic diagram of D FF from enabled SR FF
D Q(t+1)
CLK
0
1
1
X
0
1
Q(t)
0
1
comment
NC
Reset
Set
Characteristic Table
Symbol of D FF
Pin diagram of IC 7474
4. T flip-flop:
K=T
J=T
Q(t+1)= JQ`(t)+K`Q(t)
Q(t+1)= TQ`(t)+T`Q(t)
Characteristic equation
Logic diagram of T FF from enabled JK FF
CLK
T
Q(t+1)
comment
0
1
1
X
0
1
Q(t)
Q(t)
Q`(t)
NC
NC
Toggle
Characteristic Table
Symbol of T FF
Part A: Practice Procedure:
1. Implement active high SR flip flop using IC’s and breadboard and verify the truth table.
2. Implement D, JK and T Flip-Flops using IC’s and breadboard and verify the truth table.
Conclusions: Basic memory elements are implemented and verified.
3
Module: Logic Design Lab
Name: ...................................
University no:………………………..
Group no: …………………………….
Lab Partner Name:
Mr. Mohamed El-Saied
Part B: Lab. Exercise:
Students are directed to do the following exercise.
1. Draw the logic diagram for active high clocked SR flip-flop (NOR-Implementation). Give the
characteristic table and derive its characteristic equation using key-map. What is the problem
encountered in this flip-flop.
2. Show how to modify clocked SR flip-flop to get J-K flip- flop. Give the characteristic table and write
its characteristic equation.
3. Construct D-type and T-Type flip-flops from J-K flip- flop. Give the characteristic table and write its
characteristic equation. Differentiate between them.
4. What is the function of IC’s 7474 and 7476? Illustrate the logic symbol and pin-description for each.
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