M74HC73
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
■
■
■
■
■
■
■
HIGH SPEED :
fMAX = 80MHz (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC =2µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 73
DESCRIPTION
The M74HC73 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C2MOS technology.
Depending on the logic level applied to J and K
inputs, this device changes state on the negative
going transition of clock input pulse (CK). The
)
(s
t
c
u
DIP
PACKAGE
TUBE
t
e
l
o
s
b
O
TSSOP
u
d
o
r
P
e
ORDER CODES
DIP
SOP
TSSOP
)
s
(
ct
SOP
M74HC73B1R
M74HC73M1R
T&R
M74HC73RM13TR
M74HC73TTR
clear function is accomplished independently of
the clock condition when the clear input (CLR) is
taken low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
d
o
r
P
e
t
e
l
o
s
b
O
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/11
M74HC73
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1, 5
1CK, 2CK
2, 6
12, 9
13, 8
14, 7, 3, 10
11
4
NAME AND FUNCTION
Clock Input
Asynchronous Reset
1CLR, 2CLR
Inputs
1Q, 2Q
True Flip-Flop Outputs
Complement Flip-Flop
1Q, 2Q
Outputs
1J, 2J, 1K, Synchronous Inputs
2K
Flip-Flop 1 and 2
GND
Ground (0V)
Vcc
Positive Supply Voltage
)
s
(
ct
TRUTH TABLE
INPUTS
OUTPUTS
CLR
J
K
CK
X
Q
L
H
e
t
e
ol
L
X
X
H
L
L
Qn
H
L
H
L
H
H
L
H
H
H
H
X
X
LOGIC DIAGRAM
s
(
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
O
)
H
Qn
Pr
FUNCTION
CLEAR
NO CHANGE
H
----
L
----
Qn
Qn
TOGGLE
Qn
Qn
NO CHANGE
bs
X : Don’t Care
2/11
Q
u
d
o
M74HC73
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Supply Voltage
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
± 50
mA
500(*)
mW
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
)
s
(
t
-65 to +150
300
c
u
d
°C
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
e
t
e
l
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature
Input Rise and Fall Time
o
s
b
tr, tf
s
(
t
c
O
)
u
d
o
o
r
P
Value
Unit
2 to 6
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
r
P
e
t
e
l
o
s
b
O
3/11
M74HC73
DC SPECIFICATIONS
Test Condition
Symbol
VIH
Parameter
High Level Input
Voltage
Low Level Input
Voltage
VIL
VOH
VOL
II
High Level Output
Voltage
Low Level Output
Voltage
ICC
Input Leakage
Current
Quiescent Supply
Current
t
e
l
o
s
b
O
4/11
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Typ.
Max.
1.5
3.15
4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
0.5
1.35
1.8
1.9
2.0
1.9
1.9
IO=-20 µA
4.4
4.5
4.4
4.4
du
IO=-20 µA
5.9
6.0
5.9
IO=-4.0 mA
4.18
4.31
4.13
5.68
5.9
6.0
IO=-5.2 mA
2.0
IO=20 µA
0.0
0.1
4.5
IO=20 µA
0.0
0.1
o
r
P
6.0
IO=20 µA
0.0
0.1
4.5
IO=4.0 mA
0.17
6.0
IO=5.2 mA
0.18
6.0
6.0
5.8
V
5.63
V
)
s
(
ct
IO=-20 µA
4.5
Max.
0.5
1.35
1.8
4.5
6.0
Unit
1.5
3.15
4.2
2.0
V
4.10
5.60
0.1
0.1
0.1
0.1
0.1
0.1
0.26
0.33
0.40
0.26
0.33
0.40
VI = VCC or GND
± 0.1
±1
±1
µA
VI = VCC or GND
2
20
40
µA
)
(s
t
c
u
d
o
r
P
e
Value
e
t
e
l
b
O
so
V
M74HC73
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time (CK - Q)
tPLH tPHL Propagation Delay
Time (CLR - Q)
fMAX
Maximum Clock
Frequency
tW(H)
tW(L)
Minimum Pulse
Width (CK)
tW(L)
Minimum Pulse
Width (CLR)
Minimum Set-up
Time
ts
Minimum Hold
Time
th
tREM
e
t
e
ol
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Min.
Typ.
Max.
75
15
13
125
25
21
145
29
25
6
30
35
30
8
7
42
14
12
54
18
15
15
60
80
18
6
6
21
7
6
30
8
6
O
)
s
(
t
c
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
95
19
16
155
31
26
180
36
31
4.8
24
28
let
25
7
6
Unit
Max.
110
22
19
190
38
32
220
44
37
ns
ns
)
s
(
ct
u
d
o
r
P
e
75
15
13
75
15
13
75
15
13
0
0
0
75
15
13
o
s
b
du
o
r
P
Minimum Removal
Time
TA = 25°C
VCC
(V)
tTLH tTHL Output Transition
Time
Value
4
20
24
95
19
16
95
19
16
95
19
16
0
0
0
95
19
16
ns
MHz
110
22
19
110
22
19
110
22
19
0
0
0
110
22
19
ns
ns
ns
ns
ns
CAPACITIVE CHARACTERISTICS
s
b
O
Symbol
Parameter
Test Condition
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
10
CIN
Input Capacitance
5.0
5
CPD
Power Dissipation
Capacitance (note
1)
5.0
35
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + I CC/2 (per FLIP/
FLOP)
5/11
M74HC73
TEST CIRCUIT
)
s
(
ct
u
d
o
r
P
e
CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
t
e
l
o
WAVEFORM 1: MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle)
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
6/11
s
b
O
M74HC73
WAVEFORM 2 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
WAVEFORM 3 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH, SETUP AND HOLD TIME
(f=1MHz; 50% duty cycle)
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
7/11
M74HC73
Plastic DIP-14 MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
1.39
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
)
s
(
ct
20
E
8.5
e
2.54
e3
15.24
u
d
o
0.335
7.1
I
5.1
1.27
s
(
t
c
2.54
e
t
e
ol
bs
O
)
3.3
Z
Pr
0.100
F
L
0.787
0.600
0.280
0.201
0.130
0.050
0.100
u
d
o
r
P
e
t
e
l
o
s
b
O
P001A
8/11
M74HC73
SO-14 MECHANICAL DATA
mm.
DIM.
MIN.
TYP
A
inch
MAX.
MIN.
TYP.
a1
1.75
MAX.
0.1
0.068
0.2
a2
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
b1
0.19
0.25
0.007
C
0.5
0.018
)
s
(
ct
0.010
0.019
c1
45° (typ.)
D
8.55
8.75
0.336
E
5.8
6.2
0.228
e
1.27
e3
7.62
F
3.8
4.0
4.6
5.3
L
0.5
)
(s
e
t
e
l
so
b
O
1.27
S
Pr
0.344
0.244
0.050
G
M
u
d
o
0.68
0.300
0.149
0.157
0.181
0.208
0.019
0.050
0.026
8° (max.)
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
PO13G
9/11
M74HC73
TSSOP14 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
c
0.09
0.20
0.004
D
4.9
5
5.1
0.193
E
6.2
6.4
6.6
0.244
E1
4.3
4.4
4.48
1
e
bs
0.65 BSC
K
0°
L
0.45
let
o
s
b
0.60
s
(
t
c
0.75
du
ro
P
e
0.0089
0.197
0.201
0.252
0.260
0.173
0.176
0.0256 BSC
0°
8°
0.018
0.024
0.030
u
d
o
r
P
e
A
O
)
8°
0.012
t
e
l
o
0.169
)
s
(
ct
A2
A1
b
O
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
10/11
M74HC73
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom
© http://www.st.com
11/11