EE210: Switching Systems
Lecture 17: Designing Sequential Systems
Using Flip Flops
Prof. YingLi Tian
Nov. 14/16, 2016
Department of Electrical Engineering
The City College of New York
The City University of New York (CUNY)
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Designing Sequential Systems

Goal: Given a problem statement – a verbal
description of the intended behavior of the
system, design a block diagram of the
system using the available components and
meeting the design objectives and
constraints.
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Steps of Designing Sequential Systems -- 1
Step 1: From a word description, determine
what needs to be stored in memory, that is,
what are the possible states.
Step 2: If necessary, code the inputs and
outputs in binary.
Step 3: Derive a state table to describe the
behavior of the system.
Step 4: Use state reduction techniques to find
a state table that produces the same
input/output behavior, but has fewer states.
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Steps of Designing Sequential Systems -- 2
Step 5: Choose a state assignment, that is,
code the states in binary.
Step 6: Choose a flip flop type and derive the
flip flop input maps or tables.
Step 7: Produce the logic equation and draw a
block diagram (as in the case of
combinational systems).
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Design Example 1

A system with one input x and one output z such
that z=1 if and only if x has been 1 for at least
three consecutive clock time.

Step 1 – 3: create state table
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Design Example 1: state assignments
q has 4 states: A, B, C, D.
Need two 1-bit memories q1
and q2 to represent all the
states.
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Design Example 1: Truth table
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Design Example 1: output map and equations
q1* = xq2 + xq1
q1*
q2*
q2* = xq2´ + xq1
z = q1 q2
Conclusion: need 4 two-input AND gates, 2 two-input OR gates.
q1* and q2* share one gate: xq1
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Designing Systems Using Flip Flops
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Method 1: truth table-based method
Method 2: map-based method
Method 3: quick method (only works for
JK flip flops).
We use previous example:
 A system with one input x and one output z such
that z=1 if and only if x has been 1 for at least
three consecutive clock time.
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Designing based on Truth Table
– D Flip Flops
From Slide 8:
D 1 = x q2 + x q 1
D2 = x q´2 + x q1
q1* = xq2 + xq1
q2* = xq2´ + xq1
z = q1 q2
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D Flip Flops
The output depends only on the input. The D flip flop behavior table:
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Designing based on Truth Table
– D Flip Flops
D1 = q1* = xq2 + xq1
D2 = q2* = xq2´ + xq1
z = q1 q2
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JK Flip Flop

JK flip flop is a combination of the SR and T flip
flops. It behaves like a SR flip flop (J as S, K as
R). However, if J=K=1, it behaves like a T flip
flop.
q* = Jq´ + K´q
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Designing by JK Flip Flops
q* = Jq´ + K´q
From Slide 8:
q1* = xq2 + xq1
q2* = xq2´ + xq1
z = q1 q2
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Designing by JK Flip Flops
J1 = xq2
J2 = x
K1 = x´
K2 = x´ + q´1
z = q1q2
Conclusion: need 2 two-input AND gates, 1 two-input OR gate,
and a NOT gate for x´.
A volunteer to draw the circuit diagram!!
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Designing by SR Flip Flops
q* = S + R´q
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Designing by SR Flip Flops
R1 = x´
z = q1q2
S1 = xq2
S2 = xq´2
R2 = x´ + q´1q2
Conclusion: need 4 two-input AND gates, 1 two-input OR gate,
and a NOT gate for x´.
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Designing by T Flip Flops
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Designing by T Flip Flops
T1 = x´q1 + xq´1q2
T2 = x´q2 + xq´2 + xq´1q2
z = q 1q 2
Conclusion: need 4 two-input AND gates, 1 three-input AND gate,
1 two-input and 1 three-input OR gate, and a NOT gate for x´.
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Quick method of implementation
by using JK Flip Flops
Using SR flip flop
q* = S + R´q
Using JK flip flop with
more Xs than SR.
q* = Jq´ + K´q
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Quick method of implementation
by using JK Flip Flops
If q = 0, we have q* =J
q* = Jq´ + K´q
If q = 1, we have q* =K´
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Quick method of implementation
by using JK Flip Flops
Computation of J1 and K1
J1 = xq2
K1 = x´ both J1 and K1 do not depend on q1.
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Quick method of implementation
by using JK Flip Flops
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J2 = x, K2 = x´ + q´1 , both J2 and K2 do not depend on q2.
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Quick method of implementation
by using JK Flip Flops
J1 = xq2 , K1 = x´ or K´1 = x
J1 = xq2
J2 = x
z = q1q2
K1 = x´
K2 = x´ + q´1
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Quick method of implementation
by using JK Flip Flops
J2 = x, K2 = x´ + q´1
J1 = xq2
J2 = x
z = q1q2
K1 = x´
K2 = x´ + q´1
If q = 0, we have q* =J;
q* = Jq´ + K´q
If q = 1, we have q* =K´
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Practice 1:

A system with one input x and one output z such
that z=1 if and only if x has been 1 for at least
three consecutive clock time.

Step 1 – 3: create state table
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Use a different state assignment
q has 4 states: A, B, C, D.
Need two memories q1 and
q2 to represent all the states.
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Designing by Using JK Flip Flops
q* = Jq´ + K´q
Using quick method
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Practice 2:

A system with one input x and one output z such
that z=1 if and only if x = 1 and has been 1 for at
least two consecutive clock time.
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Step 1 – 3: create state table
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Announcement
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HW6 is due today
HW7 is out today, due on Nov. 21, 2016
Practice: P430 Example 7.4
Read Chapter 7.1


Designing Sequential Systems using Flip
Flops
Next Class (Chapter 7.2 and 7.3)

Design of Counters
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