Australian Journal of Basic and Applied Sciences, 5(11): 375-382, 2011
ISSN 1991-8178
Hardware Prototyping of Root Raised Cosine FIR Filter for 2x2 MIMO Channel
Sounder
1
M. Habib Ullah, 1Mandeep Sing, 1Sumazly Sulaiman, 2M. Shamim Shumon, 1M. Islam
1
Dept. of Electrical, Electronic and System Engineering Faculty of Engineering and Built
Environment UniversitiKebangsaan Malaysia.
2
Institue of Science & Technology, National University of Bangladesh
Abstract: A root raised cosine (RRC) finite impulse response (FIR) digital filter using Xilinx system
generator blockset in simulink environment is presented in this paper. The RRC filter is designed and
implemented as a part of BPSK transmitter for CDM based 2x2 MIMO channel sounder. The role of
the filter in the transmitter is pulse shaping. Pulse shaping is needed to specify the bandwidth of band
limited base band communication system. In this paper, a 32 order square root FIR digital filter is
designed and implemented in Xilinx FPGA.
Key words: Root Raised Cosine Filter, Xilinx FPGA, Pulse Shaping, MIMO Channel Sounder.
INTRODUCTION
Advances in wireless communications have introduced tremendous demands in the antenna technology
(Azim et al., 2010a-b; Azim et al., 2011a-b; Islam et al., 2009a-d; Islam et al., 2010b-c; Liu et al., 2011;
Mobashsher et al., 2010; Shakib et al., 2010). It also paved the way for wide usage of mobile phones in modern
society resulting in mounting concerns surrounding its harmful radiation (Faruque et al., 2010a-c; Faruque et al.,
2011a-b; Islam et al., 2009e; Islam et al 2010a). Multiplexing multicarrier communications have become very
important for the future communications networks. Numerous researches on antenna technology are ongoing
both in industry and academia to provide reliable communication systems [M. W. Numan, M. T. Islam, 2010].
Digital filter is a vital part of multicarrier communication. Digital filtering can be performed by using either
infinite impulse response (IIR) orfinite impulse response (FIR) filter. FIR filters have both advantages and
disadvantages compared to (IIR) filters. FIR filters have the primary advantages, such as: (i) exact linear phase
can be designed, (ii) always stable, (ii) efficient realization in hardware. The primary disadvantage of FIR filters
is that they often require a much higher filter order than IIR filters to achieve a given level of performance
[9,10]. Correspondingly, the delay of these filters is often much greater than for equal performances IIR filter. A
few popular applications for FIR filters are: (i) Echo cancellation in Video processing (ii) Speech synthesis (iii)
Waveform synthesis (iv)Image enhancement in digital cameras and digital video camcorders (v) Special effects
in Reverberation/echo effect and (vi) Biomedical signal processing. FIR filtering can be performed using
various filtering structures. Among these are the direct form, transposed form and lattice structures. Each has
advantages and disadvantages when considering number of arithmetic operations, memory requirements, and
round-off error (M. Habib Ullah, 2010). FIR filters can be expressed graphical format. The equation (i) is
expressed as a difference equation, while the bottomequation (ii) is expressed as a Z-transform. Fig. 1 shows the
mathematical operation required are addition (subtraction), multiplication and delay operation.
y n
h k
n
k
(1)
(2)
There are generally five steps in the design of a digital filter: the filter requirements specification, the filter
coefficients calculation, a suitable structure filter representation, the effects of finite word length on the filter’s
performance analysis, implementation of the filter in software and/or hardware. Steps 2, 3, and 4 are usually
grouped together when using automated tools (Islam, M.T., et al., 2009d).
Corresponding Author: M. Habib Ullah, Dept. of Electrical, Electronic and System Engineering Faculty of Engineering
and Built Environment UniversitiKebangsaan Malaysia
375
Aust. J. Basic & Appll. Sci., 5(11): 375
5-382, 2011
Fig. 1: FIR
R Direct Form
mitting a sign
nal at high moodulation rate through a baand-limited chhannel can creeate intersymbbol
Transm
interferencce. As the moddulation rate in
ncreases, the ssignal's bandwiidth increases.. When the siggnal's bandwiddth
becomes larger
l
than thee channel banndwidth, the cchannel starts to introduce distortion to the
t signal. Thhis
distortion is usually seeen as intersym
mbol interferennce. The specctrum of a recctangular pulse spans infiniite
frequency. In many datta transmission
n applicationss, the transmittted signal muust be restrictted to a certaain
bandwidth. This can bee due to eitherr system desiggn constraints. In such insttances, the inffinite bandwiddth
gular pulse is not acceptablee. The bandwiidth of the rectangular pulsee can be limiteed,
associated with a rectang
however, by
b forcing it too pass throughh a filter. The act of filteringg the pulse cauuses its shape to change froom
purely recttangular to a smooth contouur without shaarp edges. Theerefore, the acct of filtering rectangular daata
pulses is offten referred too as pulse shaping (F. Xu, 20005 &C. L. Cheen, 1999).
R
FIR Filteer:
Designof RRC
The overall FIR filtter design is illlustrated in F
Fig. 2. Initiallyy, random num
mber generatorr is used as daata
d with LS codee generator in order
o
to implem
ment the compplete transmitteer. Xilinx systeem
source whiich is replaced
generator is
i used to creaate Netlist for all simulnk bllocks. FDA toool block used for graphical user
u
interface to
provide performance specifications, succh as magnitudde and phase reesponse plots aand pole-zero plots.
p
R filter system
Fig. 2: FIR
mulink design of RRC filterr (Faruque, M.R.I., et al., 20010b) by usingg Xilinx Systeem
Fig.3 shows the Sim
Generator blocks. System
m Generator is a system leveel modeling too
ol that facilitatees FPGA hardware design annd
o
to providde a powerful modeling enviironment that is well suited to
extends Simulink in variious ways in order
d
The tool provides high-level abstraactions that are automaticallyy compiled intto a netlist codde
hardware design.
and also FPGA
F
configurration bitstream
m file at the puush of a button
n. System Geenerator block sets allow us to
construct bit-accurate
b
andd cycle-accuratte models of ann FPGA circuitt in Simulink.
Fig. 4 presents the reesponse of RR
RC FIR filter inn FDA tool. Inn the output ressponse of the design
d
frequenccy
is normalizzed between 0 and 1. The nettlist generationn of the RRC fiilter to create thhe Verilog codde is presented in
Fig. 5. Thee design param
meter specificatiion is shown inn table 1.
Aust. J. Basic & Appll. Sci., 5(11): 375
5-382, 2011
Table 1: Filteer design parameteer specification
Param
meter
Respo
onse type
Orderr
Desiggn method
Rollo
off Factor
Frequuency unit
Frequuency (Fs)
Frequuency (Fc)
Magnnitude
Specification
Raised cosinee
32
FIR (Window
w)
1.0
Mhz
40
5
Square root
Fig.3: Sim
mulink design of
o RRC FIR filtter using the coonstant multipllier block
Fig.4: Thee response of RRC
R
filter.
Aust. J. Basic & Appll. Sci., 5(11): 375
5-382, 2011
Fig. 5: Nettlist Generationn of RRC filterr.
Fpga Impllementation:
The RRC
R
FIR filter is implemented
d as a part of ttransmitter for 2x2 MIMO chhannel sounderr. The RRC filtter
is used forr pulse shaping
g purpose. The transmitter is comprised of random numbeer generator, up-sampler,
u
Rooot
Raised Cosine (RRC) fillter, and digitaal up-converterr (DUC) and digital
d
to analoog converter (116 bit DAC) annd
i configured too transmit at thhe center frequuency of 2.45 G
GHz. The LS code
c
generator is
RF transmitter. The RF is
used as the data source for the transm
mitter (Islam, M
M.T, et al., 20099b). The RF
F board is based on Sundance
w
consists of 2 separate Transceivers.
T
E
Each Transceivver can be conffigured as eitheer Transmitter or
SMT349 which
Receiver. Both
B
transceiv
vers configuredd as transmitteer for this papeer. The RF Trransmitter up-cconvert 70 MH
Hz
signal to 2.45 GHz and transmit
t
it thruu Antenna. . Thhe bandwidth of
o available haardware for thee transmission is
R
around 16 MHz. The ADC is setup too run at 30.722 MHz so thatt the DAC outtput image lies within the RF
nge centered att 70 MHz. Fig.6 shows the innstallation setupp of FPGA (SM
MT 350) and RF
R
transmitterr input BW ran
transceiverrs (SMT 349).
Control Taask:
Contro
ol Task is respponsible for reaading the contrrol data from Host
H and passees the control data
d to the ADC
C,
DAC and clock
c
synthesizers for properr operation of the data conveersion. Controll task also receeives the contrrol
data for SM
MT349 which is
i then passed thru
t
output porrt 0 on to the SMT349.
S
DAC Taskk:
This taask reads digittal data from chhannel 0 (32 bit) and send daata to DAC to converts the 16 bit digital daata
to analog. The
T DAC is coomprised of thee two channelss DAC A and DAC
D
B.
Storage Taask:
This taask stores the data
d coming on
n its input channnel 0 in a 4KB
B memory. The data stored are
a sent to outpput
channel 0.
Aust. J. Basic & Appl. Sci., 5(11): 375-382, 2011
Fig. 6: FPGA installation setup
Experimental setup:
FPGA Tasks:
There are several steps needed to perform in FPGA as shown in Fig.7 and each task is described briefly as
follows:
Fig. 7: Flowchart of FPGA Implementation steps.
BPSK Transmitter Task:
The BPSK transmitter task performed as shown in Fig.4.5. The source code is written in Verilog and
synthesized by Xilinx ISE 9.2 is used to generate the configuration file (*.cfg file).
Host Program:
The host program performs several tasks including resetting the hardware and configuring the FPGA on the
SMT368, setting up the ADC, DAC, clock synthesizer and RF SMT349. The host program handles the required
communication protocol to receive data (through USB) from FPGA and displaying the graphic data on the host
PC.
379 Aust. J. Basic & Appl. Sci., 5(11): 375-382, 2011
RESULT AND DISCUSSION
The proposed BPSK transmitter is designed using Matlab, Verilog and Xilinx system generator blocks. The
whole design is simulated as a single ISE project by using ModelSim simulation tool and compiled using ISE
9.2. The ISE project synthesized as top module Tx_lscode_top Module including two submodulelscode1 and
lscode2. The ISE project synthesis report, ModelSim simulation result and RTL illustration of top module and
sub modules are included in this section. Moreover, the Graphical User Interface (GUI) is designed by using
visual C++ to configure the transmitter.
GUI Application to Run the Constellation:
Using Reset/Prog button in the constellation screen the FPGA has been configured and the status indicates
the FPGA has been successfully configured. After successfully FPGA configured, RF setup has been done using
RF Setup button. Status shows "RF setup OK" if nothing goes wrong. ADC/DAC setup and clock is synthesized
by clicking the ADC/DAC SETUP button. Using ADCStream button data streaming is captured from the BPSK
output and displayed the constellation. Fig.8shows the GUI application to configure the transmitter in order to
visualize the constellation.
Fig.8: GUI for the transmitter
The RF board is based on Sundance SMT349 which consists of 2 separate transceivers. Each Transceiver
can be configured as either Transmitter or Receiver. In this paper, both transceivers configured as transmitter
TX1 and TX2 for this paper.
Conclusion:
In this paper, a RRC FIR filter is designed by using simulink system generator blockset and implemented in
Xilinx based FPGA as a part of BPSK transmitter for 2x2 MIMO channel sounder. The role of the filter is pulse
shaping before transmission. The bandwidth of the system is 16MHz and chip rate is 7.68 Mhz and the pulse
duration of the RRC filter is 0.13μs (Pulse duration = 1/Chip Rate). The purpose of the transmitter is to measure
the minimum and maximum delay. After design and implementation of the proposed transmitter, delay
calculated minimum 0.13μs and maximum 520 μs.
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