A Study of Tungsten Metallization for the Advanced BEOL Interconnections
James Hsueh-Chung Chen, Susan Su-Chen Fan, Theodorus E. Standaert, Terry A. Spooner,
and Vamsi Paruchuri
IBM Research at Albany Nano-Tech, 257 Fuller Road, Albany, New York 12203, USA
Tel: 518-292-7139
Fax: 518-292-7395
E-Mail: [email protected]
ABSTRACT
In this paper, a study of tungsten metallization in
advanced BEOL interconnects is presented. A mature
10 nm process is used for comparison between the
tungsten and conventional copper metallization. Wafers
were processed together till M1 dual-damascene etch
then separated for different metallization. Tungsten
metal line of 24 nm width is showing a 1.6X wire
resistance comparing to the copper metal line.
Comparable opens/shorts yield were obtained on a 0.8
M comb serpentine, Kelvin-via and 4K via chains.
Similar physical profile were also achieved. This study
has demonstrated the feasibility of replacing the copper
by tungsten at BEOL using the conventional tungsten
metallization tools and processes. This could be a costeffective solution for the low-power products.
INTRODUCTION
Tungsten is a refractory metal with high resistance
to electronmirgation and it has good gap fill capability
with chemical-vapor deposition (CVD) technology [12]. Meanwhile, not only the dry etch of tungsten [3], but
the chemical-mechanical polish of Tungsten [4] are both
mature processes. Therefore, tungsten metallization has
been a simple and reliable high volume manufacturing
technique at contact level of the CMOS technology for
many years. Unfortunately, due to its high resistivity,
tungsten is not a good candidate for the BEOL
interconnects. However, due to the surface scattering
effect when the metal width is approaching the mean
free path of 39 nm of copper, the resistivity of copper is
increased dramatically [5]. Also, the gap-fill capability
and reliability of copper metallization are all hurdles for
the extendibility of copper [6] at the advanced
technology node, such as 10 nm node. On the other
hand, tungsten has a smaller mean-free path of 19 nm
[7], as a result, the resistivity of tungsten will be close to
copper at small dimension by many predictions [8-9].
Therefore, there is an interest to understand the
feasibility of replacing copper with tungsten at the
BEOL of 10 nm node as a cost-effective solution. This
could be a significant benefit for the low power products
where the interconnect resistance is not a major concern
[10].
The metal resistance, via resistance, metal
opens/shorts and nest via chain continuity are important
criteria for the success of tungsten.
EXPERIMETNAL
In order to demonstrate the feasible of tungsten
metallization at the BEOL interconnects, a mature 10 nm
process is used as the test vehicle [11] where the mask
set is designed for immersion-DUV lithography. This
process starts from the tungsten contact level followed
by the double patterned V0 and triple patterned M1.
Wafers were built to the M1 dual-damascene etch to
ensure the same initial metal trench profile, then,
followed by the different metallization, respectively, as
shown in Fig. 1. Tungsten metallization was conducted
by using the conventional tungsten-CVD and tungstenCMP to fill in the M1 dual-damascene structure. All the
tools and processes are the similar to contact. The wire
resistance was measured from a 1000 µm long line. A
0.8 M long comb-serpentine pattern was used for the
metal opens and shorts measurement. Four point
Kelvin-via was used for via resistance measurement.
Finally, the continuity of M1-V0-Contact was
determined from a 4K nest via chain. Electrical test and
cross section were performed to compare the
performance of both the copper and tungsten
metallization.
RESULTS and DISCUSSION
Wire resistance and via resistance
The wire resistance of tungsten metallization on a 24
nm wide, 1000 µm long line was 1.6X to that of copper
metallization as shown in Fig. 2. Via resistance as
plotted in Fig. 3 was showing a 1.37X Kelvin-via
resistance. Even though the wire resistance of tungsten
is 60% higher than that if copper, it is interesting that the
difference is smaller for via resistance.
This is
indicating the resistivity of copper in the confined via
hole could be much higher than the prediction.
Metal opens/shorts and Via Chain continuity
As shown in Fig. 4 (a) and (b), the opens and shorts
yield of tungsten wires on a 0.8 M comb-serpentine
structure was comparable to that of copper. The leakage
current of tungsten was one order of magnitude smaller
than that of copper.
In addition, Fig. 5 (a) and (b) were showing a good
continuity on 4K via-chains. Again, the leakage current
of tungsten metallization was better.
This result which implies tungsten metallization
could has a benefit on the surface leakage control due to
its noble property.
Physical Structure
The TEM micrographs in Fig. 6 (a) and (b) showed
the comparison of copper and tungsten via chain profile.
Tungsten wire width was about 1.5 nm larger than the
copper wire. On the other hand, Copper metallization
blew up via bottom CD quite a lot where the tungsten
metallization retained a conventional via bottom profile.
This is an indication the damage during the copper
metallization.
CONCLUSION
Electromigration and gap-fill capability are
challenges for the extendibility of copper metallization
at the most advanced technology node. The barrier
metal for copper has becoming more and more
complicated. As a result, Tungsten is a good candidate
for replacing copper with its proven high volume
manufacturability
and
good
resistance
to
electromigration.
The trade-off is the high wire
resistance of tungsten. However, the resistivity between
copper and tungsten is expected to become closer as the
dimension shrunk. Therefore, tungsten could be a good
option at the BEOL for low-power products which have
a higher tolerance to the interconnect resistance.
Vol. 19, Issue 12, pp. 508-510, 1998..
[9]. Fei Liu, B. Fletcher, E. A. Joseph, Yu Zhu, J. Gonsalves, W. Price,
G. M. Fritz, S. U. Engelmann, A. Pyzyna, Zhen Zhang, C. Cabral,
and M. A. Guillorn, “Subtractive W contact and local interconnect
co-integration (CLIC)”, Proceedings of the IEEE International
Interconnect Technology Conference, pp. 1-3, Kyoto, Japan, June 315, 2013.
[10]. V. H. Nguyen, P. Christie, A. Heringa, A. Kumar, and R. Ng, "An
analysis of the effect of wire resistance on circuit level performance
at the 45-nm technology node", Proceedings of the IEEE
Interconnect Technology Conference, pp. 191-193, Burlingame, CA,
June 6-8, 2005.
[11]. James Hsueh-Chung Chen, Christopher Waskiewicz, Susan Su-Chen
Fan et al, “48 nm Pitch Copper Dual-Damascene Interconnects With
Triple Pitch Split Metal and Double Pitch Split Via”, Proc. of
Advanced Metallization Conference, pp. 30.1 – 30.3, Albany, New
York, October 2013.
ACKNOWLEDGMENTS
This work was performed by the research alliance
teams at various IBM research and development
facilities.
REFERENCE
[1]. S. D. Mehta, "Applications of CVD tungsten in VLSI circuits",
Proceedings of the IEE Custom Integrated Circuits Conference, pp.
18.1/1 - 18.1/8, San Diego, CA, May 15-18, 1989.
[2]. M. M. Farahani, J. F. Buller, B. T. Moore, and S. Garg,
"Conventional contact interconnect technology as an alternative to
contact plug (W) technology for 0.85 μm CMOS EPROM IC
devices", IEEE Transactions on Semiconductor Manufacturing, Vol.
7, Issue 1, pp. 79-86, 1994.
[3]. Thomas E. Clark, Paul E. Riley, Mei Chang, S. G. Ghanayem, Cissy
Leung, and Alfred Mak, "Integrated deposition and etchback of
tungsten in a multi-chamber, single-wafer system", Proceedings of
Seventh International IEEEVLSI Multilevel Interconnection
Conference, pp. 478 - 485, Santa Clara, CA, Jun 12-13, 1990.
[4]. T. F. McNelly, J. D. Hayden, A. H. Perera, J. R. Pfiester, C. K.
Subramanian, M. Blackwell, B. James, S. Ajuria, W. Fell, Y. C. Ku,
T. Lii, J.-H. Lin, F. Nkansah, C. Philbin, C. J. Sun, M. Thompson,
and M. Woo, "High performance 0.25 μm SRAM technology with
tungsten interpoly plug", International Electron Devices Meeting,
pp. 927-930, Washington, DC, Dec 10-13, 1995.
[5]. Qing-Tang Jiang, Ming-Hsing Tsai, and R. H. Havemann, "Line
width dependence of copper resistivity", Proceedings of the
International Interconnect Technology Conference, pp. 227-229,
Burlingame, CA, Jun 04-06, 2001.
[6]. Terry Spooner, James H. Chen, Takeshi Nogami, Ming He and
Masayoshi Tagami, “Integration Concerns for Metallization”, Invited
paper for Advanced Metallization Conference Asia Session, Tokyo,
Japan, October 23, 2012.
[7]. Dooho Choi, Chang Soo Kim, Doron Naveh, Suk Chung, Andrew P.
Warren, Noel T. Nuhfer, Michael F. Toney, Kelvin R. Coffey, and
Katayun Barmak, "Electron mean free path of tungsten and the
electrical resistivity of epitaxial (110) tungsten films", Phys. Rev. B,
Vol. 86, pp. 045432-1 - 045432-5, July 23, 2012.
[8]. Fen Chen and D. Gardner, "Influence of line dimensions on the
resistance of Cu interconnections", IEEE Electron Device Letters,
Fig. 1 Schematic shows the process flow of this study.
Wafers were processed to M1 dual-damascene
etch, then, followed by different metallization,
respectively.
Fig. 2 Wire resistance of tungsten versus copper.
Tungsten wire resistance is 1.6X higher than that
of copper.
(a)
Fig. 3 Via resistance of tungsten versus copper.
Tungsten wire resistance is 1.37X higher than
that of copper.
(b)
Fig. 5 (a) and (b) 4K via chain opens and shorts current.
Tungsten is showing a better control on leakage
current other than the copper.
(a)
(a)
(b)
Fig. 4 (a) and (b) Comb-serpentine opens and shorts
current. The leakage current of tungsten is one
order of magnitude smaller than that of copper.
(b)
Fig. 6 (a) and (b) TEM cross sectional micrographs
show the via chain profile of copper (a) and
tungsten (b). Copper metallization blows up the
via bottom CD where the tungsten metallization
retains a typical via bottom profile.