Babu Banarasi Das
University
School of Computer Applications
Course Outline & Lecture Delivery Schedule
Bachelor of Computer Applications (BCA) Syllabus
I Semester
T13: Digital Electronics
A: Introduction:
Digital logic is concerned with the interconnection among digital components and modules and is
a term used to denote the design and analysis of digital systems. The best known example of
digital system is the general purpose digital computer. The components used to construct digital
systems are manufactured in integrated circuit form. Integrated circuit contains a large amount
of interconnected digital circuits with in a single small package. Medium scale integration (MSI)
devices provide digital functions and large scale integration (LSI) devices provide complete
computer modules.
B: Objectives:
The Objective of the subject is to: 1. Provide a better understanding of Computer Organization, its designing &
implementation.
2. To study various issues concerning Organization.
C: Students Performance Evaluation Scheme:
External Semester Examination
:
50 Marks
Internal Performance Assessment
:
50 Marks
3 Sessional Tests
:
40 Marks
Attendance
:
5 Marks
Teacher Assessment
:
5 Marks
Based on Assignments, Seminars,
Group Discussions & Class Participation
D. Reading:
I-Text:
T1: M. Mano, “Digital Logic and Computer Design”, 2nd Edition, PHI
II-Reference:
R1: P. Raja, “Switching Theory”, Fourth Edition, Umesh Publication
Detailed Lecture Session Schedule
Lecture
Sessio
n No.
Topics
1.
Introduction of Digital Electronics
2.
Introduction to the number system system, (Decimal, Binary, Octal,
Hexadecimal)
Decimal To binary conversion & binary to decimal
Conversion of decimal to Octal, octal to decimal, decimal to
hexadecimal, hexadecimal to decimal
Conversion of binary to octal, octal to binary, binary to
hexadecimal, hexadecimal to binary
Conversion of octal to hexadecimal, hexadecimal to octal,
Complement(r’s complement, (r-1)’s complement)
Binary addition and substraction
Binary multiplication and division
Substraction with r’s complement & (r-1)’s complement
Binary codes, weighted codes
BCD codes and its conversion
Excess 3 codes, 8,4,2,1 concept
Different conversions using BCD
Excess 3 and 8,4,2,1 of binary
Error detection codes, odd priority check and even priority check
Types of errors, reflected codes
Hamming Codes
Logic gates AND, OR, NOT, XNOR, XOR, NOR, NAND
3.
4.
5.
6.
7.
8.
9.
13.
De’ Morgan’s theorem
Universal building blocks
Universal gates
Logical combinations
Logic circuits
Electrical circuits
Boolean Algebra Logical Statement
Compound logical statement
Boolean constant
Boolean variable
Operators
Expressions
Compound expressions
Tautologies
Fallocies
Boolean postulates
Truth table
Principal of duality Laws of Boolean algebra
Boolean theorems
Minterms, Maxterms, SOP, POS
14.
Cononical & non & cononical SOP, Adders
10.
11.
12.
T1: Chapter 1
P: 1-2
T1: Chapter 1
P: 4-10
T1: Chapter 1
P: 4-10
T1: Chapter 1
P: 4-10
T1: Chapter 1
P: 10-15
T1: Chapter 1
P: 16-20
T1: Chapter 1
P: 16-20
T1: Chapter 1
P: 26-29,
T1: Chapter 2
P: 56-57
T1: Chapter 1
P: 26-29
T1: Chapter 2
P: 34-39
T1: Chapter 2
P: 34-39
T1: Chapter 2
P: 39-41
T1: Chapter 2
P: 47-52
T1: Chapter 2
P: 47-52
15.
Half adder, full adder
16.
Encoders & Types of encoders, Decoder & Types of decoders
17.
Multiplexer, Demultiplexer
18.
19.
Introduction to K-MAP
Types of K- map
How to fill the K-MAP
How too reduce the expression using K-Map
20.
Simplification of algebraic expression
21.
Multilevel NAND & NOR
22.
Ex-OR Equivalence function, Parity checker parity generator
23.
ROM(types of ROM)
24.
PAL, PLA, Charateristics of PLA), Comaprators
25.
Introduction of sequential circuit
Block diagram of a sequential circuit
Introduction to flip-flops Basic Latch
SR Flip Flop, D Flip Flop:
Logic Diagram
Characteristic Table
Graphic Symbol
Characteristic Equation
JK Flip Flop, T Flip Flop:
Logic Diagram
Characteristic Table
Graphic Symbol
Characteristic Equation
Master Slave Flip Flop
Clocked Master Slave Flip Flop
Triggering of flip- flops:
Negative edge Triggered flip flop
Positive edge triggered flip flop
Edge triggered flip flops
Direct clear and direct preset input
Example clocked of sequential circuit
State table
Present State
Next State
Output
State Diagram(According to State Table)
State equation
How many Flip Flops Required
Flip flop Input Functions According to Equation
Flip flop input function
26.
27.
28.
29.
30.
31.
State Reduction
Input Sequence & Output Squence according to initial State
with State Diagram
State Table according to the given State Diagram
Reduction Algorithm
Reduced States according to reduction Algorithm
T1: Chapter
P: 119-123
T1: Chapter
P: 174-175
T1: Chapter
P: 172-177
T1: Chapter
P: 72-83
4
T1: Chapter
P: 72-83
T1: Chapter
P: 45-47
T1: Chapter
P: 86-93
T1: Chapter
P: 145-149
T1: Chapter
P: 182-189
T1: Chapter
P: 189-193
T1: Chapter
P: 202-205
3
5
5
3
2
3
4
5
5
6
T1: Chapter 6
P: 204-208
T1: Chapter 6
P: 209-213
T1: Chapter 6
P: 210-216
T1: Chapter 6
P: 218-222
T1: Chapter 6
P: 223-224
T1: Chapter 6
P: 224-228
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
Check the reduced State Table with the initial input Sequence
weather it is giving the same output or not
If its is giving the same output then draw the State Diagram
according to the reduced State table
State Reduction with another Example
Flip flop excitation table of SR, JK, T, D
Present State Q(t)
Next State (Qt+1)
Input S & R
Conversion flip flops (SR to D, T, JK)
Given & Required Flip Flop
Block diagram
Truth Table of required Flip Flop
Excitation Table of given Flip Flop
Conversion Table
K- Map Simplification
Flip Flop Conversion Logic
Conversion flip flops (JK to T, D to JK, D to T)
Given & Required Flip Flop
Block diagram
Truth Table of required Flip Flop
Excitation Table of given Flip Flop
Conversion Table
K- Map Simplification
Flip Flop Conversion Logic
Design procedure of sequential circuit
Steps to Design the Sequential Circuit
State Table
Excitation table
Block Diagram of sequential circuit
Design with State Equations, Design with State Equations with JK Flip
Flop
Introduction to registers
Register with parallel load
4- bit register with parallel load
Register with parallel load using D Flip Flop
Sequential logic implementation
Block diagram of Sequential Circuit
Example of sequential circuit implementation
Shift Register
Serial Transfer
Block Diagram
Timing Diagram
Shift Register (Serial transfer):
Serial in Serial out Shift Register
Serial in Parallel out Shift Register
Parallel in Serial out Shift Register
Parallel in Parallel out Shift Register
Bidirectional Shift register with parallel load
Serial Addition
Serial adder
Introduction to counters, basics Concept:
3- Bit Asynchronous Counter
4- Bit Asynchronous Counter
T1: Chapter 6
P: 224-228
T1: Chapter 6
P: 230-233
R1: Chapter 5
P: 280-283
R1: Chapter 5
P: 288-289
T1: Chapter 6
P: 233-238
T1: Chapter 6
P: 247-249
T1: Chapter 7
P: 256-261
T1: Chapter 7
P: 256-261
T1: Chapter 7
P: 261-263
T1: Chapter 7
P: 264-269
T1: Chapter 7
P: 266-268
T1: Chapter 7
P: 269-272
T1: Chapter 7
P: 243-247
45.
46.
47.
48.
49.
50.
51.
52.
Ripple Counter (binary Ripple counter )
4- Bit Ripple Counter
BCD Ripple Counter
State diagram of a decimal BCD Counter
Logic Diagram of a BCD Ripple Counter
Timing Diagram for the decimal counter
Synchronous Counter
Binary counter
Binary up down counter
4-bit synchronous binary Counter
4- up down binary Counter
BCD counter
Excitation Table for a BCD Counter
BCD Counter with parallel load
4-bit Binary Counter with Parallel Load
Timing Sequences
Word time generation
Timing signals
Circuit Diagram
Timing Diagram
Johnson counter
Ring Counter
Counter and Decoder
Sequence of Four timing Signals
Design of counters
Excitation table for a 3-bit binary Counter
Maps for a 3-bit binary Counter
Logic Diagram of a 3-bit Binary Counter
Design of counters with Example
Excitation Table
Logic Diagram of a Counter
State Diagram of Counter
T1: Chapter 7
P: 272-274
T1: Chapter 7
P: 274-276
T1: Chapter 7
P: 276-279
T1: Chapter 7
P: 280-282
T1: Chapter 7
P: 284-286
T1: Chapter 7
P: 286-289
T1: Chapter 6
P: 243-247
T1: Chapter 6
P: 243-247