ECEN 3100 Digital Logic
Prof. I.R. Jones
Laboratory Assignment: 4-Bit Multiplier
Objective: Using Verilog HDL to design a multiplier circuit that multiplies two 4-bit numbers
by adding a series of “partial products”.
Discussion: Long-hand multiplication is done by adding partial products. A partial product is
defined as
partial_product = (multiplicand  (multiplier_digit))  (radix)(position_of_multiplier_digit))
In the procedure, we first generate all of the partial products. To get the product (the result of
multiplying two numbers), we add all of the partial products. Figure 1 demonstrates the
procedure in decimal and in binary.
Decimal
12
 13
36
+ 120
156
multiplicand
multiplier
= ((12  3)  100)
= ((12  1)  101)
product
Binary
11002
multiplicand
multiplier
 11012
11002 = ((11002  1) 
000002 = ((11002  0) 
1100002 = ((11002  1) 
+ 11000002 = ((11002  1) 
100111002 = 156
20)
21)
22)
23)
Figure 1. Multiplication by addition of partial products
Note that when a number is multiplied by its radix, it is the same as shifting the number to the
left by one position. To implement this functionality in hardware requires two major circuit
components – a circuit to multiply and number by zero or one, and a 4-bit adder circuit. These
components are connected such that the circuit structurally and functionally emulates the partial
product algorithm. Figure 2 shows a block diagram of the circuit.
4-Bit Multiplicand: x3 x2 x1 x0
Multiplier Digit: y0
0 / 1 Multiplier
carry
out
4-bit Adder
4-Bit Multiplicand: x3 x2 x1 x0
Multiplier Digit: y1
4-bit Adder
4-Bit Multiplicand: x3 x2 x1 x0
Multiplier Digit: y2
Multiplier Digit: y3
sum3
sum2
sum1
0 / 1 Multiplier
carry
out
4-Bit Multiplicand: x3 x2 x1 x0
sum3
0 / 1 Multiplier
carry
out
4-bit Adder
sum3
sum2
sum1
sum0
0 / 1 Multiplier
4-bit Adder
8-Bit Product
Figure 2. Block diagram of 4-bit multiplier circuit.
0
sum0
sum2
sum1
sum0
Assignment: The assignment is in two parts.
1. Do the tutorial on implementing circuits on a FPGA using Verilog programming. Have the
instructor or T.A. verify your work on the tutorial and sign-off this portion of the laboratory.
2. Create a new project and in Verilog, implement the 4-bit multiplier that uses the addition of
partial products method. Use proper programming methodology by modularizing the
structure of your program (i.e. partition your program into connected modules or functions).
The block diagram of the circuit (Figure 2) shows that there are several repeatable structures
in the circuit. A Verilog program that consists of a single monolithic module will not be
given full credit for this assignment. The interface to this circuit will be 8 switches and 8
LEDs. The 8 switches will be used for the multiplier Y = y3y2y1y0 and multiplicand X =
x3x2x1x0. The 8 LEDs are used to display the product result. Have the instructor or T.A.
verify and sign-off on your circuit.
In your lab report compare and contrast Verilog programming versus schematic capture. What
are the advantages of Verilog programming versus schematic capture? What are the
disadvantages?
Also in your lab report answer the following
1. How does the design scale? In other words, as the number of bits are increased for X and
Y, how will the amount of hardware in the implementation of the circuit change?
2. How would you estimate the computation time for this circuit?
3. Is there a point at which this method is not a good implementation of a multiply
algorithm? Explain your answer.
ECEN-3100
4-Bit Multiplier
Sign-off
Please attach this sheet to your lab report.
Name ______________________________________
Name ______________________________________
Verilog tutorial complete.
_____________________________________________
T.A./Instructor Signature
________________________
Date
4-bit multiplier circuit verified.
_____________________________________________
T.A./Instructor Signature
________________________
Date
Comments
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