REM
Radiation Effects Module
The REM Radiation Effect Module allows Atlas 2D/3D and Victory 3D simulators
to model total dose, dose rate and SEU effects in semiconductors through the
generation of defect states, fixed charge, and charge transport within insulating
materials.
• Irradiate feature allowing arbitrary radiation sources
• e+/h+ generation and recombination rates as functions of electric field
• Photocurrent flow inside device structure
• Carrier transport and trapping in silicon dioxide
• Interface to Athena process simulator for modeling process-dependent defect distributions and
photocurrent evaluation
• Charge generation as a function of photocurrent density and LET
• Self consistent solution of device equations with charge generation in insulator layers
• Flexible C-interpreter routines to prototype custom models for photogeneration, recombination, and
charge trapping
• Displacement Damage Model
Schematic of an ECL D-Flip-Flop used in shift registers.
Output waveform for D-Flip-Flop circuit for an LET=40MeV
-cm2/mg at 5.37ns with switching current of 0.6mA.
Single Event Effects (SEE)
• Advanced physics based models for SEU analysis
• Simultaneous simulation of multiple SEU tracks at
any angle
• MixedMode simulation allows both transistor and
circuit level SEU effects to be modeled together
• Macro model transient currents source
development
Definition of the SEU strikes incorporates generation of e-h
pairs as a function of time, distance from the particle track
center as well as distance from the particle entry point. Entry
and exit points are arbitrary and multiple particles strikes are
supported.
Sample 2D cross section taken from the full 3D structure
used in the SEU strike simulation.
• Verilog-A supports the development of compact
device models that can be compiled into the
SmartSpice circuit simulation family
Normalized collector current for different particle strikes
with LET values of 20, 40, 60 and 80 MeV-cm2/mg.
DC sweep circuit of an NMOS-SOI device with compact device
model written in Verilog-A.
Total Dose
NMOS device response to Total Ionizing Doses of 100K, 500K
and 1 Meg-Rad(Si).
• User-defined models for carrier generation rates depending on radiation-type and dose-rate
• User-defined models for electron-hole-pair recombination (Germinate and Columnar recombination
supported)
• Carrier (electron and hole) and proton transport in insulators
• Carrier trapping and detrapping in insulators
• User-defined models for carrier trapping rates as function of carrier velocities, carrier concentrations, current
densities, and electric field
• Support for dispersive transport using multiple-trapping and detrapping
Dose Rate
• Defined flow from TCAD model of device to SPICE model for dose-rate photocurrent’s
• Ability to investigate process parameter and biasing variations of generated dose-rate photocurrents
• Ability to select mobility and recombination models
• Ability to provide uniform and non-uniform carrier generation within the device
Displacement
Damage
• Fluence dependent defects model
Schematic of an SOI operational amplifier.
Dose rate response of the OP-Amp to a 5E9 rad(Si)/sec 25 ns
pulse.
Integrated Flow
• REM allows various radiation effects (Total Dose, Dose Rate, SEE) to be modeled at the transistor level
• The compact model development environment allows users to create physics-based SPICE behavioral
models in Verilog-A based on measured data or simulation results from REM
• SmartSpice RadHard simulates radiation effects at the circuit level and can accommodate in excess of 8
million active transistors
• Gateway Schematic Entry is tightly coupled with SmartSpice and Verilog-A to enable the transition of the
radiation data into circuit representation
• Silvaco’s Schematic Driven Layout (SDL) interface allows for the automated transfer of Gateway
schematics into Expert layout cells
• Expert Layout Editor is capable of handling the largest analog, mixed signal, and digital designs
in a hierarchical environment with built in features (all angle drawing, guard rings, and others) to
accommodate Radiation Hardening by Design (RHBD)
• Guardian DRC/ERC/LVS physically checks the Expert layout to ensure the foundry specified design rules
have been met and also supports additional user defined radiation rules
• Clever Parasitic Extraction provides the critical parasitic data using 3D field solvers to extract the
interconnect analysis, and then back annotates the parasitics into SmartSpice for design closure
• This multi-level modeling approach enables radiation analysis at the transistor, circuit and finally at the
system level
• All of our tools are compatible with industry standard interfaces for interoperability with other commercial tool
flows (EDIF™, HSpice™, PSpice™, GSDII™, Dracula™, Diva™, and Calibre™)
PARASITIC EXTRACTION
MATERIALS
PROCESS MODELING
PHYSICAL VERIFICATION DRC/LVS
Defect Input to
Atlas
Clever
Athena
DEVICE MODELING
Guardian DRC/LVS
INTEGRATED ENVIRONMENT
FOR
IC LAYOUT
RADIATION HARDENED
DESIGN
Expert
Atlas
COMPACT MODEL
GENERATION
BEHAVIORAL MODELING
SPICE SIMULATION
SCHEMATIC CAPTURE
Verilog-A
Verilog-A
Gateway
SmartSpice
Silvaco Inc.
4701 Patrick Henry Drive, Bldg. 2
Santa Clara, CA 95054 USA
WWW.SILVACO.COM
Mobile: 408-318-1977
[email protected]
Rev 052416_11