EE 280
Introduction to Digital Logic Design
Lecture 25.
Latches and Flip-Flops
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Enabled or Clocked S-R Latch
A more sophisticated flip-flop
• an input is effective only when enabled by a 1 input at terminal C
• in a digital system composed of many elements, it is usually necessary for the
outputs of all elements to be synchronized
• synchronizing signal may come from a clock (ck), and therefore the name of the
enabling terminal
• in a clocked system, transitions do not run wild through a circuit; instead,
changes occur in an orderly, one-step-at-a-time fashion
• in addition to the synchronous inputs R and S, there may be asynchronous inputs
to clear and preset the flip-flop
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1
The Data Latch
To avoid the ambiguous state where R = 1 and S = 1 simultaneously
• connect an inverter between the R and S terminals and use only one input signal;
number of terminals is reduced (an advantage for IC)
When the clock line is high, the output Q follows the input D
• when flip-flop is enabled, the input data is transferred to the output line
After the clock line goes low, no change in Q is possible, and the output is
"latched" at the previous data value.
This data latch is widely used as an element in digital systems
• for example, a set of eight such latches could "remember" the eight digits
representing a number or an instruction
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The Data Latch Timing Diagram
C
t
D
t
Q
t
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The D Flip-Flop
In digital systems it is sometimes desirable to delay the transfer of data from
input to output
• e.g., we may wish to maintain a present state at Q while we read in a new state that
will be transferred to the output at the appropriate time.
D (for delay) flip-flop is a refinement of the
data latch that has a second R-S flip-flop
• the data latch is enabled when the clock signal
goes low, but the following R-S flip-flop is
enabled when clock goes high.
• Q1 follows D when C is low, but any change in
the output of the combination Q = Q2 is
delayed until the next upward transition of ck
• this is an edge-triggered flip-flop
• Q1 followed while ck is low, then, on the
leading edge of the clock pulse, the value of D
is transferred to output Q
• on the logical symbol the small triangle
indicates an edge-triggered device (data is
EE280 Lecture 25
read when the clock is low)
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The D Flip-Flop
If D changes at most once following each clock pulse, the output of the flipflop is the same as the D input, except that changes in the output are
delayed until after the trailing edge of the clock pulse as illustrated.
Timing diagram for clocked edge-triggered D flip-flop
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The Toggle Flip-Flop (T Flip-Flop)
delay
S
Q
R
Q’
T
delay
Change of state each time T = 1.
Problem: If T is too long, a continuous toggle of the flip-flop, i.e., if T > delay
then it will change state again.
T
Q
Q+
Characteristic equation:
0
Q+ = R’Q + S = (TQ)’Q + TQ’
= (T’+Q’)Q + TQ’ =
= T’Q + TQ’
Q+ = T + Q
0
1
0
1
1
1
0
} toggle
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The J-K Flip-Flop
Combines S-R and T flip-flops
• J and K inputs can = 1 simultaneously
J
KQ
0
1
00
0
1
01
1
1
11
0
0
10
0
1
Characteristic equation:
Q+ = R’Q + S = (KQ)’Q + JQ’
= (K’+Q’)Q + JQ’
Q+ = K’Q + JQ’
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The Clocked J-K Flip-Flop
Eliminates problem of delay and "long" I/P pulses
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Master-slave (falling-edge) J-K flip-flop
The J-K Flip-Flop Symbols
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The (raising-edge) J-K Flip-Flop
J
KQ
0
1
00
0
1
01
1
1
11
0
0
10
0
1
clock
J
K
Q
tp
tp
t1
tp
t2
t3
tp – short delay to change value after rising edge of cl
at t1 – Q changes to 1 since J=1, K=0, Q=0 before rising cl edge
at t2 – Q changes to 0 since J=0, K=1, Q=1 before rising cl edge
at t3 – Q changes to Q’ since J=1, K=1 before rising cl edge
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The Clocked T Flip-Flop (edge triggered)
With the J and K inputs tied together and brought out to a single input
terminal, the J-K unit becomes a T or toggle flip-flop
• for T = 0 (J=K=0) the clock pulse has no effect on output Q
• for T = 1 (J=K=1) the flip-flop toggles each time ck goes to low
The timing diagram shows that for t held high
• the output is a square wave of half the frequency of the clock;
• the device is a frequency driver
• If the CK input responds to a sequence of events, the T flip-flop "divides by two".
T
0
1
00
0
x
C
01
1
x
T
11
x
0
Q
10
x
1
TQ
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The Clocked T Flip-Flop (edge triggered)
Notice that it takes two clock pulses to cause the flip-flop to make one
complete transition from Q low to Q high and back to Q low
• If a train of clock pulses is applied to the input at frequency f, the output of Q
would be a pulse train with a frequency of f/2
• The circuit is often called a divide-by-2 or binary
• Any number of toggle flip-flops can be cascaded for division by successive powers
of 2. The circuit is counting by twos.
C
T
Q
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The Clocked T Flip-Flop (edge triggered)
Divide by 2 by 4 by 8 by …..
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Summary of Latch and Flip-Flop Characteristics
Device
Characteristic Equation
SR Latch
Gated SR
D Latch
SR Flip-flop
D Flip-flop
JK Flip-flop
T Flip-flop
Q+ = S + R’Q
Q+ = SC + R’Q + C’Q
Q+ = DC + C’Q
Q+ = S + R’Q
Q+ = D
Q+ = K’Q + JQ’
Q+ = TQ’ + T’Q
(clocked)
Q+ = Q’
T Flip-flop
(edge-triggered)
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