Fall 2010 Digital Logic Homework 4 Solution Due on Thursday, Dec 30 (Sections 1 & 2); Wednesday, Dec 29 (Section 3) 1. (15 pts) Any type of flip flop can be implemented using any other type of flip flop and some additional gates: (a) (5 pts) Construct a JK flip‐flop using a D flip‐flop and minimal combinational logic. (b) (5 pts) Construct a D flip‐flop using a JK flip‐flop and minimal combinational logic. Page 1 of 4 (c) (5 pts) Construct a T flip‐flop using a JK flip‐flop. 2. (20 pts) Analyze the following sequential circuit. CLK is the clock signal. (a) (8 pts) Fill in the state table: (b) (8 pts) From the state table, draw the state diagram. Label your states with the current values of Q (that is, 0 or 1). The arrows between should be labeled with input (xy) / output(s) Page 2 of 4 (c) (4 pts) Starting in state Q = 0, which states are not reachable, if any? 3. (20 pts): Sequential Circuit Analysis Below is a diagram made of two JK flip‐flops. There are no inputs and the outputs are just the flip‐flop states Q1 and Q0 themselves. (a) (12 points). Fill in the rest of the state table below for this circuit. (b) (8 points). Draw the state diagram for this circuit. Since there are no inputs or outputs, you do not need to label your state transition arrows. Page 3 of 4 4. (24 pts): Sequential Circuit Analysis II Analyze the following circuit diagram made of two JK flip‐flops and answer the questions that follow. There is one input variable X and two state variables Q1 and Q2 for FF1 and FF2 respectively. (a) . (18 points) Fill in the rest of the following table. (b) . (6 points) If the initial state is 11, does the circuit have any unused state? If yes, name the unused state. If no, justify that there is no unused state. 5. Sequence Recognizer (24 points) In this problem you will be designing a sequential circuit for a sequence recognizer. You will develop a state diagram with one input variable X and one output variable Z. The output is 1 if and only if the last three input bits are 001 or 010. Note that sequences may overlap. Sample input: 0 0 1 0 1 0 1 1 0 0 1 0 0 0 Sample output: 0 0 1 1 0 1 0 0 0 0 1 1 0 0 Page 4 of 4 (a) Draw the state diagram. Label each arc with X/Z. Label the initial state with A and other states with B, C, D, etc. as required. Explain the purpose of each state. Use a minimum number of states. (b) Implement this state diagram using the minimum number of D flip‐flops. Draw the state table for this state diagram and derive Boolean expressions for the inputs to the D flip‐flops and the output of the sequential circuit. You do not need to draw the circuit. Page 5 of 4 6. Counters ‐ Up/Down Counter (10 points) Implement a counter to count 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, . using the standard four bit counter. You may use gates and other combinatorial circuit elements. Make your design as simple as possible. The pins D2, D1, D0 should be counting the above sequence. Note: Do NOT use or alter the UP/DOWN or LD pin. 7. Counters ‐ Skip Counter (12 points) Use the standard counter (shown below) to implement a 4‐bit (unsigned) counter that skips 3 and 4. That is, it should count from 0, 1, 2, 5, 6, 7 ... Page 6 of 4