University of California at Berkeley
College of Engineering
Department of Electrical Engineering and Computer Science
EECS 150
Pister
Spring 2006
Homework 7: 10.8, 10.9, 10.11, 9.17
SOLUTIONS
Problem 10.8
Random Access Memories
A microprocessor with an 8-bit wide data bus uses RAM chips of 4096 x 1-bit capacity. How many
chips are needed and how should their address lines be connected to provide a memory capacity of 16
K-bytes (1 byte = 8 bits).
4096 / 8 bit = 512 Bytes per RAM Chip.
16,384 / 512 = 32 RAM Chips
The microprocessor wants to access a byte of data at one time.
4096 bit = 212
therefore there are 12 address lines per each RAM Chip
14
16,384 byte= 2
therefore need 14 address line to access each byte
Problem 10.9
Random Access Memories
Consider a 1-megabit dynamic memory component. The memory is organized into 512 rows of 2048
bits each. Assume that every bit must be refreshed within 4 ms.
refresh operation be scheduled?
How frequently should a row
If the memory has an 80 ns access time, approximately what fraction
of memory access must be dedicated for refresh?
Since you can refresh an entire row at once,
Refresh Time = 4ms / 512 rows = 7.8125 us
Bit Refresh Cycles = Refresh Time / 80ns = 97.65 cycles
Meaning once in every 97 cycles a refresh must be performed or ~1% of the time.
Problem 10.11
Random Access Memories
Consider the read and write timing of the 2114 memory component in Figures 10.24 and 10.25. What
is the minimum clock width for the overlapping clocks generated by the memory controller that will
still meet the memory’s timing specification?
Justify your answer.
The write cycle time is 200ns and the write pulse width time is at least 100ns. Therefore each grid in
Figure 10.30 is 50ns, which would meet the timing requirements of the above or each clock phase is
200 ns.
As a check, this clock phase width also satisfies the timing requirement for a read.
Problem 9.17
Xilinx CLB
The basic function generator within the Xilinx CLB can implement any combinational logic function of
four inputs. This is equivalent to how many 2-input gates?
Explain how you derived your answer.
16 other ways to do it.
Note:
The following
one possible
way to implement
a 4-LUT. can
There
may2be
A two-input
gate canisgenerate
24 = 16 functions.
A four input-gate
generate
= 65536
functions.
Implementation
using PLA:
Each CLB contains four 4-LUTS. I will implement each 4-LUT with a PLA structure.
Each 4-LUT implements a 4 input function. The truth table has exactly 16 entries.
By looking at the K-map, there are at most 8 sum terms. (if every adjacent entry is different then, there
will be exactly 8 terms in the sum of products).
So each 4-LUT needs eight 8-input AND gates and one 8-input OR Gate
Each 8-input AND gates require seven 2-input AND gates to make.
F, G8-input
and H OR
can gate
each requires
implement
16 functions
each.gates
Since
the output of F and G are connected to H,
Each
seven
2-input OR
to make.
the entire block can generate (4*4)4 = 65536 functions. Therefore this is equivalent to 3 2-input logic
The total number of 2-input gates per 4-LUT is = 8*7 + 7 = 63.
gates.
There are four 4-LUTs per CLB, so the total number of 2-input gates per CLB is 4*63 = 252.