Flip-Flop
p
p Summary
y
D flip-flop
SR flip-flop
JK flip-flop
fli fl
T flip-flop
p p
Latch VS Flip-Flop
p
p
D Latch
D flip-flop
Simple cell
Master-slave
Level trigger
Edge trigger
Pulse clock
Clock, 50% duty
Race condition
Cost
D FF
D FF
D FF
D FF
SR FF
SR FF
JK FF
JK FF
T FF
T FF
T FF
T FF
ALL
Using
g Xilinx ISE 9.2i
Project with Schematic
1. New Project/Open Project
2. New Source/Add Source
3 Schematic
3.
4. Synthesize
5 C
5.
Create
t S
Symbol,
b l S
Symbol
b l Wi
Wizard
d
6. Implement Design
7. Create Test Bench WaveForm
8. Simulate Post-Place & Route Model
Using
g Xilinx ISE 9.2i
Project with Schematic
Save All files
Out-of-Date Symbols
Crash, recover?
.SCH
SCH schematic file
.SYM symbol file
.TBW
TBW Testbench
T tb
h file
fil