University of Florida
Department of Electrical & Computer Engineering
Page 1/12
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
Instructions:
 Turn off all cell phones, beepers and other noise making devices.
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Show all work on the front of the test papers. Box each answer. If you need more room, make a clearly
indicated note on the front of the page, "MORE ON BACK", and use the back. The back of the page will not
be graded without an indication on the front.
You may not use any notes, HW, labs, books, or calculators.
This exam counts for 20% of your total grade.
Read each question carefully and follow the instructions.
You must pledge and sign this page in order for a grade to be assigned.
The point values for problems may be changed at prof’s discretion.
Truth tables and voltage tables must be in counting order.
Label the inputs and outputs of each circuit with activation-levels.
For each mixed-logic circuit design, equations must not be used as replacements for circuit elements. Label
inputs of each gate with the appropriate logic equations.
Boolean expression answers must be in lexical order,( i.e., /A before A, A before B, & D3 before D2).
For K-maps, label each grouping with the appropriate equation.
Put your name at the top of this test page (and, if you remove the staple, all others). Be sure your exam
consists of 12 distinct pages. Sign your name and add the date below.
Good Evening!
Welcome!
Good luck &
Go Gators!!!
PLEDGE: On my honor as a University of Florida student, I certify that I have neither given
nor received any aid on this examination, nor I have seen anyone else do so.
SIGN YOUR NAME
DATE (9 November 2010)
Regrade comments below: Give page # and problem # and reason for the petition.
Page
Available
2-3
4
5
6-8
9
10
11-12
15
10
13
20
12
11
19
TOTAL
100
Points
University of Florida
Department of Electrical & Computer Engineering
Page 2/12
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
[15%] 1. Design a system that sequences through the following outputs: 3710, 5510, 510, 3710, 5510, 510,
etc. The system must asynchronously reset to output the “3710” when Start (active-high)
2 min
goes true. When the sequence output is 5510, the active-low output Z should be true. Use a
JK-FF for the most significant bit of the design, a T-FF for the least significant bit, and a DFF for any other bits you might need. Note: All the given FFs have active-low
asynchronous clear and set inputs. Use the minimum number of flip-flops and then try to
minimize the number of other SSI gates necessary to solve this problem.
a) Complete the next-state truth table. You may not need all the rows and/or columns.
5 min
b) Find the required simplified (MSOP or MPOS) equations.
5 min
University of Florida
Department of Electrical & Computer Engineering
Page 3/12
5 min
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
1. c) Design the complete circuit, minimizing the total number of components, but using the
JK-FF and T-FF (and D-FF(s), if necessary) as described previously. All inputs and
outputs of the circuit should be clearly indicated coming into or out of the below box.
Your design must include the circuitry necessary to asynchronous re-start the system at
output “3710” when the Start (active-high) signal goes true and show the active-low
output Z when the output is “5510.”
University of Florida
Department of Electrical & Computer Engineering
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Page 4/12
[10%] 2. Design a 3-bit universal bi-directional
shift register that performs the
7 min
following functions. Use only flipflops and other non-memory SSI or
MSI gates.
Exam 2
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
S1 S0 Action
0 0 Hold value (i.e., no shift)
0 1 Shift right with sign extension
Rotate left, with the least significant bit taking
1 0
the previous value’s most significant bit
1 1 Load a new value
University of Florida
Department of Electrical & Computer Engineering
Page 5/12
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
[6%]
3. Answer the following questions about a state machine designed with one EEPROM, one J-K
flip, one T flip-flop, and all other flip-flops of type D.
(2%)
a) What is the size of the EEPROM [addresses x data bits] if the state machine has 3 inputs,
4 outputs, and 5 states?
2 min
(2%)
2 min
(2%)
2 min
[2%]
b) What is the size of the EEPROM [addresses x data bits] if the state machine has 1 inputs,
4 outputs, and 9 states?
c) What is the size of the EEPROM [addresses x data bits] if the state machine has 1 inputs,
0 outputs, and 3 states?
4. What is the major difference between a Moore output and a Mealy output.
2 min
[5%]
4 min
5. Draw a switch circuit for an active-high input
signal, X(H). Draw the switch in the true position.
Do NOT draw a layout. Draw a timing diagram of
the bouncing that will occur on this non-debounced
switch circuit as the switch goes from the true to
false positions.
H
X(H)
L
University of Florida
Department of Electrical & Computer Engineering
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Page 6/12
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
[20%] 6. Given as many 64x4 EEPROMs as needed and as many 64x8 SRAMs as needed, design the
memory module described below, with an active-low chip enable, CE. The device should
2 min
begin with 64x8 of EEPROM and then immediately follow with 128x8 of SRAM. The
64x8 of EEPROM must start at address $40 and the first address of the 128x8 of SRAM
must immediately follow the last EEPROM address. Add the minimum number of
memory devices and the minimum number of additional SSI components required.
( %)
a) Draw vertical and horizontal lines in the box below and label each resulting box with the
memory type and size, using only the defined types and sizes given above. Also, fill in
the subscript on the D at the top left and the maximum address at the bottom right.
5 min
Data Bits
D__
D0
$40
$40
Increasing Addresses
_____ = max address
( %)
5 min
b) What is the address and data ranges for each of the memory components drawn above (in
binary and in hex)?
64x4 EEPROM(s):
64x8 RAM(s):
University of Florida
Department of Electrical & Computer Engineering
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Page 7/12
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
(
%) 6. c) Design the required memory device below. Add the minimum number of additional
memory components and SSI gates necessary (no MSI gates or PLDs). Add address
5 min
subscripts as needed and cross out unneeded address and data pins. Use labels instead
of wires for the design. Also, write the equations for each CS; but you must make a
complete circuit diagram. Show all connections with either labels or wires, just as in
Quartus. Don’t forget the system’s active-low chip enable, CE.
A0
A1
A2
A3
A
A
A
A
A
A
A
A
A
A
A
A
CE(L)
R/W
64x 4 EEPROM
A0
A1
A2
A3
A
A
A
A
A
A
A
A
A
A
CS
D0
D1
D2
D3
64x 8 SRAM
A0
A1
A2
A3
D0
A
D1
A
D2
A
D
A
3
A
D4
A
D5
A
D6
A
D7
A
A
WE
CS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
University of Florida
Department of Electrical & Computer Engineering
Exam 2
Page 8/12
(
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
%) 6. d) Fill the unused memory space, starting at address 0, with more SRAM(s). Draw the
memory module from parts a-c as a single device, add the necessary 64x8 SRAM(s), and
add the connections and SSI components needed to complete the design. Add address
subscripts as needed and cross out unneeded address and data pins. Use labels instead
of wires for the design. Also, write the equations for each CS; but you must make a
complete circuit diagram. Show all connections with either labels or wires, just as in
Quartus. Don’t forget the system’s active-low chip enable, CE.
5 min
A0
A1
A2
A3
A
A
A
A
A
A
A
A
A
A
A
A
Memory for parts a‐c
A0
A1
A2
A3
D0
A
D1
A
D2
A
D3
A
A
D4
A
D5
A
D6
A
D
A
7
A
R/W
CE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
CE(L)
R/W
64x 8 SRAM
A0
A1
A2
A3
D0
A
D1
A
D2
A
D3
A
A
D4
A
D5
A
D6
A
D7
A
A
WE
CS
64x 8 SRAM
A0
A1
A2
A3
D0
A
D1
A
D2
A
D3
A
A
D4
A
D5
A
D6
A
D7
A
A
WE
CS
University of Florida
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Department of Electrical & Computer Engineering
Exam 2
Page 9/12
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
[12%] 7. The following figure shows a simplified circuit diagram. Assume that all of the
inputs and outputs are active-high. The ROM contents are given in the below
10 min
table; note that the values in the table are in octal [base 8]. (This problem is
very similar to a problem in homework 8 that was also done in class on two
separate occasions.)
(10%)
a) Derive the ASM chart for this circuit. Show ALL work, i.e., use at least
part of the below blank table. (Do not miss part b below.)
Y1
D4
Q1
Q0
X
CLK
A1
A0
Y0
D3
A2
8x5
ROM
D2
J
D1
K
Q
D
Q
D0
CLK
CLK
Contents of
the ROM
Addr Value
Octal Octal
0
@06
1
@06
2
@22
3
@11
4
@24
5
@31
6
@30
7
@16
Q1
Q0
.
.
.
.
.
.
.
.
.
.
.
.
(2%)
b) If input X in part a is changed to active-low, describe all the changes in the truth table
and ASM (if any); you may want to redraw the ASM (with the changes).
University of Florida
Department of Electrical & Computer Engineering
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Page 10/12
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
[11%] 8. Answer the following questions about the ASM chart for the 2010 UF Football Team
Offense controller. The following signals are active-low: Brantley and Run; all the other
signals are active-high. An asynchronous Reset (not shown) will put the machine in the
Start state.
(4%)
4 min
a) Draw the voltage timing diagram (showing all the relevant signals) when in the Start
state, Open goes from true to false to true to false before the
next active-clock edge (and stays there through the clock edge).
What is the next state?
Next state is __________________
(7%)
6 min
Open
b) Complete the next-state truth table. Draw the minimum
number of rows necessary. The state bits should be entered in
counting order. Use wildcards (*) for inputs or don’t cares
(X) for outputs.
Blitz
Q1
0
Q0 Q1+
0
Q0+
Brantley
Pass
Burton
Run
Reed
.
.
.
.
.
.
.
.
.
.
.
.
.
.
University of Florida
Department of Electrical & Computer Engineering
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Page 11/12
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
[18%] 9. A block diagram of your lab 6 is shown here, along with two tables from the same handout.
4
INPUT Bus
REGA Bus
REGB Bus
OUTPUT Bus
MSA1
MSA0
4
MUX A’s
MUX B’s
4
CLK
REG A
REGA Bus
4
4
MSC2:0
(6%)
6 min
3
MSB1
MSB0
4
MSC
REG B
CLK
REGB Bus
4
Combinatorial Logic
Cin
MSA1:0/
MSB1:0
00
01
10
11
Cout
4
MUX C’s
OUTPUT Bus
000
001
010
011
100
101
110
111
Bus Selected as Input
to Combinatorial Logic
INPUT Bus
REG A Bus
REG B Bus
Output Bus
Action
REGA Bus to OUTPUT Bus
REGB Bus to OUTPUT Bus
complement of REGA Bus to OUTPUT Bus
bit wise AND REGA/REGB to OUTPUT Bus
bit wise OR REGA/REGB Bus to OUTPUT Bus
sum of REGA Bus & REGB Bus to OUTPUT Bus
shift REGA Bus left one bit to OUTPUT Bus
shift REGA Bus right one bit to OUTPUT Bus
without sign extension
4
a) Assume that you can add small additional circuits to the circuit described with the above
block diagram. The purpose of these additional circuits is to know when RegA is equal
to zero (output is ZA) and to know when there would be an overflow when addition is
used (output is V). Design these two circuits. Show ALL your work. Assume all signals
are active-high.
University of Florida
Department of Electrical & Computer Engineering
Page 12/12
EEL 3701—Fall 2010
Tuesday, 9 November 2010
Exam 2
Dr. Eric M. Schwartz
____________________________
Last Name, First Name
(5%)
9. b) Find the average of the two numbers, $C and $5. (Your algorithm should still work even
if the two numbers are changed.) Store the result in A. Describe what is accomplished in
4 min
each step. Use the minimum number of states. [In future, change numbers to $A and $5.]
#
1
2
3
4
5
6
7
1.
2.
3.
4.
5.
6.
7.
(8%)
5 min
MSA MSB MSC Input Cin RegA RegB Output Cout RegA+ RegB+ Output+ Cout+
0000 1111
c) Use the table below to SUBTRACT $5 from $C. (Your algorithm should still work even
if the two numbers are changed.) Store your solution in register B. Describe what is
accomplished in each step. Use the minimum number of states.
# MSA MSB MSC Input Cin RegA RegB Output Cout RegA+ RegB+ Output+ Cout+
0000 1111
1
2
3
4
5
6
7
8
1.
2.
3.
4.
5.
6.
7.
8.