DIGITAL ELECTRONICS
EXTC – SEMESTER 3
Module No.
1
Topics
Number Systems and Codes
Hours
4
Number System
Conversion of Decimal to any base Part 1 , Conversion of Decimal to any base Part 2
Conversion of Any base to decimal Part 1
hexa-octa-binary conversion
binary to grey
Codes Part 1 , Codes Part 2 , Codes Part 3
Representation of -ve numbers
1'C method Part 1 , 1'C method Part 2
2'C method
Octal Arithmetic 7'C method Part 1 , Octal Arithmetic 7'C method Part 2
Octal Arithmetic 8'C method Part 1 , Octal Arithmetic 8'C method Part 2
9'C Method Part 1 , 9'C Method Part 2
10'C Method Part 1 , 10'C Method Part 2
Ex-3 to BCD conversion Part 1 , Ex-3 to BCD conversion Part 2
4 Bit Adder Subtractor Part 1 , 4 Bit Adder Subtractor Part 2
Excess 3 Arithmetic Addition and Subtraction Part 1 , Excess 3 Arithmetic Addition and Subtraction Part 2
Excess 3 Arithmetic Addition and Subtraction Part 3
Binary to Grey code
Division in Binary and Octal
Hexadecimal Arithmetic- 15C Part 1 , Hexadecimal Arithmetic- 15C Part 2
Hexadecimal Arithmetic- 16C
2
Logic Gates and Combinational Logic Circuits
Logic Families Part 1 , Logic Families Part 2 , Logic Families Part 3
Characteristics of digital ICs Part 1 , Characteristics of digital ICs Part 2 , Characteristics of digital ICs Part 3
Logic Gates Part 1 , Logic Gates Part 2 , Logic Gates Part 3 , Logic Gates Part 4
Universal gates Part 1 , Universal gates Part 2
Demorgan's theorem Part 1 , Demorgan's theorem Part 2
Sum Of Product
Product Of Sum Part 1 , Product Of Sum Part 2
K-map Part 1 , K-map Part 2 , K-map Part 3 , K-map Part 4
16
5 Variable K-map Part 1 , 5 Variable K-map Part 2 , 5 Variable K-map Part 3
Characteristics of digital ICs Part 1 , Characteristics of digital ICs Part 2 , Characteristics of digital ICs Part 3
Don't care conditions Part 1 , Don't care conditions Part 2
Quine mac Clusky Part 1 , Quine mac Clusky Part 2 , Quine mac Clusky Part 3 , Quine mac Clusky Part 4
Comparison of CMOS and TTL family
Tri State or Three State Devices part 1 , Tri State or Three State Devices part 2
Variable Entered Mapping(VEM) Part 1 , Variable Entered Mapping(VEM) Part 2
Half adder and Subtractor
Full adder Part 1 , Full adder Part 2
ExOR as inverter
Boolean Laws
Full subtractor Part 1 , Full subtractor Part 2
Universal gates Part 1 , Universal gates Part 2
Carry Look Ahead Adder Part 1 , Carry Look Ahead Adder Part 2
Implement Ex-OR logic using NOR gate
Implementing SOP equation using NOR gates
4 bit full adder
BCD adder using IC7483 Part 1 , BCD adder using IC7483 Part 2
BCD arithmetic Part 1 , BCD arithmetic Part 2
Sum Of Product
Magnitude comparator Part 1 , Magnitude comparator Part 2
MUX Part 1 , MUX Part 2
MUX Tree Part 1 , MUX Tree Part 2
5 Variable K-map Part 1 , 5 Variable K-map Part 2 , 5 Variable K-map Part 3
DEMUX
DEMUX Tree Part 1 , DEMUX Tree Part 2
Don't care conditions Part 1 , Don't care conditions Part 2
Encoder Part 1 , Encoder Part 2
Decoder Part 1 , Decoder Part 2
BCD or HEX to 7 segment Part 1 , BCD or HEX to 7 segment Part 2
Seven segment common anode common cathode
Parity generators and checkers
Canonical or standard POS form , Canonical or standard SOP form
Hazards and Hazard covers Part 1 , Hazards and Hazard covers Part 2
Hazards and Hazard covers Part 3 , Hazards and Hazard covers Part 4
Design of a Combinational circuit-1 part 1 , Design of a Combinational circuit-1 part 2
MUX-IC-74151
Difference between MUX and DEMUX part 1 , Difference between MUX and DEMUX part 2
DECODER IC-74138 and DEMUX or DECODER IC-74139
3
Sequential Logic Circuits
Introduction to Flip-Flop
S-R Flip-Flop Part 1 , S-R Flip-Flop Part 2
Preset and Clear Part 1 , Preset and Clear Part 2
J-K flip flop Part 1 , J-K flip flop Part 2
Race around in JK
D and T flip flop Part 1 , D and T flip flop Part 2
Characteristic equations of Flip-Flop
Excitation table for flip-flops Part 1 , Excitation table for flip-flops Part 2 , Excitation table for flip-flops Part 3
Converting one flip-flop to another SR to JK conversion
Diff between asynchronous And synchronous counter
Asynchronous counter Part 1 , Asynchronous counter Part 2 , Asynchronous counter Part 3
Asynchronous Down counter Part 1 , Asynchronous Down counter Part 2 , Asynchronous Down counter Part 3
MOD N counter Part 1 , MOD N counter Part 2 , MOD N counter Part 3
Synchronous counter (mod 6) Part 1 , Synchronous counter (mod 6) Part 2
Skipping state counter Part 1 , Skipping state counter Part 2 , Skipping state counter Part 3
Shift Registers Types and Design Part 1 , Shift Registers Types and Design Part 2 , Shift Registers Types and Design Part 3
Shift Registers Types and Design Part 4 , Shift Registers Types and Design Part 5
Bidirectional shift register Part 1 , Bidirectional shift register Part 2
Ring Counter Part 1 , Ring Counter Part 2
Johnson or Twisted ring or Moebius Counter Part 1 , Johnson or Twisted ring or Moebius Counter Part 2
What are state machines & their types Part 1 , What are state machines & their types Part 2
Working of Mealy machine Part 1 , Working of Mealy machine Part 2
NOR latch-memory cell
Working of Moore machine
Edge triggered flip flops using differentiator
Characteristic equation
Universal shift register Part 1 , Universal shift register Part 2
Universal shift register IC7495
Pattern generator or Sequence Generator using Flip-Flops
Pattern generator or Sequence Generator using Shift Register
16
IC 7474 dual D-FF
IC 7476 Dual JK-FF
Difference between Registers and Counters
Lock Out Condition
Action on unused states or Bushing technique Part 1 , Action on unused states or Bushing technique Part 2
Action on unused states or Bushing technique Part 3 , Action on unused states or Bushing technique Part 4
IC 7490 as a Decade Counter Part 1 , IC 7490 as a Decade Counter Part 2
IC 7492 modulo 12 counter
IC 7493 4-bit binary counter
Maximum Operating Frequency of Asynchronous Counter
Bidirectional shift register Part 1 , Bidirectional shift register Part 2
Problems based on Shift Registers
Finite State Machines (FSM) part-1 , Finite State Machines (FSM) part-2
Pattern detector or Sequence detector using State Machine Part 1 , Pattern detector or Sequence detector using State Machine Part 2
State reduction by row implication Part 1 , State reduction by row implication Part 2 , State reduction by row implication Part 3
4
Different types of Memory
6
Classification of Memories part 1 , Classification of Memories part 2
Types of ROM part 1 , Types of ROM part 2
RAM ROM
STATIC RAM and DYNAMIC RAM
EEPROM EPROM
Erasable-Non erasable Volatile-Non volatile memory
5
Introduction to Programmable Logic Devices
Introduction to VHDL Part 1 , Introduction to VHDL Part 2 , Introduction to VHDL Part 3
VHDL data types Part 1 , VHDL data types Part 2
Concurrent and Sequential Statements(VHDL) Part 1 , Concurrent and Sequential Statements(VHDL) Part 2
Entity and Architecture Part 1 , Entity and Architecture Part 2
Modelling Styles in VHDL Part 1 , Modelling Styles in VHDL Part 2 , Modelling Styles in VHDL Part 3
Modelling Styles in VHDL Part 4 , Modelling Styles in VHDL Part 5
Introduction to PLDs
PROM PLA PAL Part 1 , PROM PLA PAL Part 2
Implement using PLA Part 1 , Implement using PLA Part 2
3- Bit Binary to Grey converter using PLA
PLA based Problem Part 1 , PLA based Problem Part 2
10