Semiconductor Technology
Research, Development, &
Manufacturing: Status,
Challenges, & Solutions
C. R. Helms*
Past President & CEO
International SEMATECH
*Professor Emeritus,
Stanford Univ.
Semiconductor Technology
Research, Development, &
Manufacturing: Status,
Challenges, & Solutions
A New Paradigm in the Making?
C. R. Helms*
Past President & CEO
International SEMATECH
*Professor Emeritus,
Stanford Univ.
Agenda
• Semiconductor Revenue Growth: Yes!
• Realize Which Roadmap?
• Technology Challenges
• R&D Cost
• • Slide 3
Agenda
• Semiconductor Revenue Growth: Yes!
– Historical Perspective & Extrapolation
• Realize Which Roadmap?
– End Equipment & Product
– Cost per Function
• Technology Challenges
–
–
–
Mask Availability, Cost, Cycletime
Post – 193nm Exposure Technology
New Materials
• R&D Cost
– How Many Si Tech R&D Centers Can the Industry
Support?
– R&D Foundries, Partnerships, & Alliances Win!
• • Slide 4
Semiconductor Industry Revenue
Growth Summary
• 17% CAGR in the 70’s and 80’s
• Drove High Rates of Capital Investment and
R&D
– In Turn Drove Better Penetration of Existing
Markets and the Opening of New Ones
• In Turn Drove Revenue Growth
• This is a Cyclical Growth Industry with a 5
5-Year Period
• Maturation is Occurring
– But not that Fast!
• • Slide 5
Projections from a Historical Study
of Industry Growth Trends
20+%
1000
h
t
w
e
o
d
r
a
G
c
e
e
g
D
a
e
r
e
h
10%
v of t
A
t
i
d
g
17% i
n
E
D
e
le th
b
u gh 16%
o
D ou
r
h
T
Revenue ($B)
Models Based on Growth of
Auto Industry 1900 - 2000
14%
100
10
1
1970
History
Model
Pessimistic
Optimistic
Cyclical Model
1975
1980
1985
1990
1995
2000
2005
2010
Year
• • Slide 6
Agenda
• Semiconductor Revenue Growth: Yes!
– Historical Perspective & Extrapolation
• Realize Which Roadmap?
– End Equipment & Product
– Cost per Function
• Technology Challenges
–
–
–
Mask Availability, Cost, Cycletime
Post – 193nm Exposure Technology
New Materials
• R&D Cost
– How Many Si Tech R&D Centers Can the Industry
Support?
– R&D Foundries, Partnerships, & Alliances Win!
• • Slide 7
Roadmap Hierarchy
End Equipment (PCs, DVDs, Hand-helds, Wireless)
Products (µPU, DRAM, DSP, Baseband)
Modules (Logic, Memory, Analog)
Specifications (VDD, Freq., Pwr.,
Cost, Lifetime)
Requirements
ITRS
Layout/Architecture (Random,
Gate Array, Logic-Based,
Memory-Based)
Materials/ Structures
(Cu, Low K, SOI,
½ Pitch)
Solutions
Processes/Tools
(193nm,
CMP )
• • Slide 8
Too Much Focus on the Lower
Level “REQUIREMENTS” can
Drive Unprofitable
Investments, i.e.
Low K Interconnects
Commodity DRAM Product
Roadmap
Capacity (MBits)
100000
10000
Commodity DRAM
Doubles Every 24 Mos.
Doubles Every 18 Mos.
1000
100
10
1994
1999
2004
2009
2014
Year
• • Slide 10
Commodity DRAM & Embedded
SRAM Product Roadmap
Capacity (MBits)
100000
10000
Commodity DRAM
Doubles Every 24 Mos.
Doubles Every 18 Mos.
1000
100
10
1994
Embedded SRAM
Doubles Every 24 Mos.
Doubles Every 18 Mos.
1999
2004
2009
2014
Year
• • Slide 11
Manufacturing Cost per Function
Roadmaps
•
Driven by Transistors per Area and Cost per Area
22-Year
-Year Cycle
Cycle
33-Year
-Year Cycle
40%
25%
Average Cost per Unit Area
Increase – Constant Wafer Size
8%
4%
Average Cost Reduction for Wafer
Size Conversion Every 10 Years
4%
4%
27%
21%
Annual Transistor per Unit
Area Increase
Predicted Annual Cost per
Function Decrease
2-Year Cycle Wins!
• • Slide 12
Validated ISMT Cost per Function Model
Slope Change in 1998 due to 22-Year
-Year Cycle
300mm Cross
-Over Predicted in 2004
Cross-Over
Cost / Function
20% per Year
Reduction
Leading Edge
Logic Products
0.35 µm
Y3
0.18 µm
Y2
0.25 µm
Y3
0.13 µm
Y2
27% per Year
Reduction
1995
1997
1999
2001
0.13 µm
300mm
90 nm
Y3
2003
2005
Years
• • Slide 13
Major Technology Challenge: The
Sub – ½ Wavelength Red Zone
500
CD < λ/2
Node (nm)
400
CD < λ/3
300
248 nm
h
g
i
H
g
n
i
v
i
r
D
s
a
M
t
s
o
C
k
193 nm
200
157 nm
100
0
1994
1998
2002
EUV
2006
2010
2014
Year
• • Slide 14
Agenda
• Semiconductor Revenue Growth: Yes!
– Historical Perspective & Extrapolation
• Realize Which Roadmap?
– End Equipment & Product
– Cost per Function
• Technology Challenges
–
–
–
Mask Availability, Cost, Cycletime
Post – 193nm Exposure Technology
New Materials
• R&D Cost
– How Many Si Tech R&D Centers Can the Industry
Support?
– R&D Foundries, Partnerships, & Alliances Win!
• • Slide 15
Mask Issues
• Phase Shift & OPC Requires 2x+ Resolution
Improvement
• Infrastructure Development Cost not
Supported by Revenue
• Database Size Exploding
• Cost Going up 2x per Generation
– Manufacturing
130nm
$ 600K
–
90nm
$1200K
–
65nm
$2400K ?
• • Slide 16
Mask Cost Analysis 130nm to 90nm
Only Manufacturing Considered
Cost per Equivalent AT Wafer
$100,000
Full Custom Advanced
Technology
Previous Node Full
Custom Technology
$10,000
Cross-Over
at 500 Wafers
$1,000
10
100
1000
10000
Advanced Technology Equivalent Wafers
• • Slide 17
Smart Gate Arrays Become
More Attractive
Cost per Equivalent AT Wafer
$100,000
Full Custom Advanced
Full Custom Advanced
Technology
Technology
Previous Node Full
Custom Technology
Previous Node Full
Advanced
Technology Std
Custom Technology
Block + Gate Array
$10,000
Cross-Over at
1500 Wafers
$1,000
10
100
1000
10000
Advanced Technology Equivalent Wafers
• • Slide 18
Summary of Top Technical
Challenges
• Mask Availability, Cost, and Cycletime
– Especially for Custom Products
• Post 193nm Litho Exposure Tools
– 157nm in Mainstream Production in 2006/2007
– EUV in Mainstream Production in 2009/2010
• New Materials
– Low K’s
– High K’s
– Memory Materials
• • Slide 19
Summary of Top Technical
Challenges
• Mask Availability, Cost, and Cycletime
– Especially for Custom Products
• Post 193nm Litho Exposure Tools
– 157nm in Mainstream Production in 2006/2007
– EUV in Mainstream Production in 2009/2010
• New Materials
– Low K’s
– High K’s
– Memory Materials
• • Slide 20
Agenda
• Semiconductor Revenue Growth: Yes!
– Historical Perspective & Extrapolation
• Realize Which Roadmap?
– End Equipment & Product
– Cost per Function
• Technology Challenges
–
–
–
Mask Availability, Cost, Cycletime
Post – 193nm Exposure Technology
New Materials
• R&D Cost
– How Many Si Tech R&D Centers Can the Industry
Support?
– R&D Foundries, Partnerships, & Alliances Win!
• • Slide 21
The New Economy for Microelectronics
• A New Factory (Fab) Runs 130nm Technology with
Cu Wiring at 300mm
• At a Capital Cost of $2B - $4B
– Increasing at a Rate of 15% per Year
• Technology R&D to Support 22-Year
-Year Major & 11-Year
-Year
Minor Product Cycles
• At a Cost of > $500M per Year for a Tier 1 Logic
Manufacturer
– Increasing at a Rate of > 20% per Year
• • Slide 22
Table Stakes for Independent
Semiconductor Manufacturer
• Cap Ex of $1B per Year
or Min. of 20% of
Revenues
– Implies Revenues of
$5B/yr
• Technology R&D
Investment of $500M
per Year
– If Requirement of <5%
of Revenues for IDM
Implies Revenues of
$10B/yr
• • Slide 23
R&D Partnership Risks & Rewards
• Rewards
– Faster Speed of Execution
– Lower Costs
• Risks
– Sacrifice of IP & Potential Competitive
Advantage
– Cultural, Geographic, and NIH Factors
can Slow Progress
– Divergence of Interests
• • Slide 24
Summary
• Semiconductor Revenue Growth: Yes!
– > 10% CAGR Through the Decade
• Realize Which Roadmap?
– End Equipment & Product
– Cost per Function
• Technology Challenges
–
–
–
Mask Availability, Cost, Cycletime
Post – 193nm Exposure Technology
New Materials
• R&D Cost
–
–
Consolidation of Si Tech R&D Centers Required
R&D Foundries, Partnerships, & Alliances Win!
• • Slide 25
Addenda
Killer App for the Future?
• Enabler Products
– Broadband
– 3+G Wireless
Silicon Core CMOS
– The Platform of
Choice
• Voice Recognition
– No Keyboards
• BioMedical Electronics
– Reduced Cost of Health Care
• Enabler Technologies
– MEMS ((MicroElectroMechanicalSystems)
MicroElectroMechanicalSystems)
– NanoTechnology - NanoElectronics
– Biotechnology - BioElectronics
• • Slide 28