Connector for
IEEE802.3bj MDI and
Future Multi-hundred Gb/s System
Takeshi Nishimura (Nish) : Yamaichi Electronics
Rev. B (Corrected page 9)
May 2012
IEEE 802.3 Interim in Minneapolis
1/12
Proposal Background
• QSFP28 has been adapted as a baseline proposal for a type of MDI
for 100GBASE-CR4
• CFP-MSA is in process to finalize CFP2 CFP4 specification for 4x28G
application
• Mechanical features and SI performance of CFP4 fit to MDI
• CFP2 and CFP4 are considered as a candidate of future generation
of multi hundred Gb/s system
• CFP4 should be recognized as a MDI option on 802.3bj
2/12
CFP4 Overview
• Comparison between others
Category
CFP
Host rates max.
11.2G
Total # of pins
148
TX + RX (Diff. Pairs)
10+10, 11+11, 12+12
REFCLK (Diff. Pairs)
1
Monitor Clocks (Diff. Pairs)
2
Ports in 364mm faceplate
4
module width (mm)
82 (76 main top)
module length (mm)
145
module main body height (mm)
13.6
CFP2
28G
104
4+4, 8+8, 10+10
1
2
8
41.5
106
12.4
CFP4
28G
56
4+4
1
1
16
21.7
88
9.5
QSFP28
28G
38
4+4
0
0
18
18.3
74
8.5
3/12
CFP4 Overview
• CFP4 has plug connector on its mating interface which provides mating accuracy
and helps to achieve high speed performance
4/12
CFP4 Overview
• Surface mount receptacle connector
• Connector cover work for EMI noise shielding, and protects receptacle
connector from mechanical stress
Connector Cover
Cage
Receptacle
5/12
CFP4 Overview
• 16 CFP4 fits in 365mm faceplate
6/12
CFP4 Pin Assignment Advantage
• QSFP28: High speed signals are located on both top and bottom row
(2 top + 2 bottom)
• CFP4: All 4 high speed signals are located on top row of the connector
- Possible simple board layout to achieve best channel performance
HS Signal Only Top
Top
HS Signal Both
Bottom
CFP4 Pin Assignment
Top
QSFP28 Pin Assignment
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
TX3n
TX3p
GND
TX2n
TX2p
GND
TX1n
TX1p
GND
TX0n
TX0p
GND
(REFCLKn)
(REFCLKp)
GND
RX3n
RX3p
GND
RX2n
RX2p
GND
RX1n
RX1p
GND
RX0n
RX0p
GND
Bottom
`
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3.3V_GND
3.3V_GND
3.3V
3.3V
3.3V
3.3V
3.3V_GND
3.3V_GND
VND_IO_A
VND_IO_B
TX_DIS
RX_LOS
GLB_ALRMn
MOD_LOPWR
MOD_ABS
MOD_RSTn
MDC
MDIO
PRTADR0
PRTADR1
PRTADR2
VND_IO_C
VND_IO_D
VND_IO_E
GND
(MCLKn)
(MCLKp)
GND
7/12
(dB)
Insertion Loss
QSFP28 SI Performance
(Actual measurement data at Yamaichi eQSFP+)
-0.52 dB
Top side adjacent differential signals
(dB)
(dB)
Return Loss
Cross-talk of Top side
-19.5 dB
-39.0 dB
8/12
(dB)
Insertion Loss
CFP2 CFP4 SI Performance
(Simulation data at latest Yamaichi design)
-0.36 dB
Top
Bottom
Adjacent differential signals on both top and bottom side
(dB)
Return Loss
(dB)
-30
Cross-talk
-39.0 dB
-40
-21.4 dB
-50
-60
-70
-80
-90
-100
-110
Rev. B
9/12
CFP2 / CFP4 Channel SI Performance Simulation
Up To 50GHz
CFP2 CFP4 CONNECTOR
･2 adjacent high speed on top side
VIA
VIA
HOST BOARD
PLUG BOARD
･Board material = N4000-13si(ε=3.2,tanδ=0.007)
･Board material = N4000-13si(ε=3.2,tanδ=0.007)
･Trace length = 4” and 7”
･Trace length = 1.25”
･Trace geometry = Stripline
･Trace geometry = microstrip
･Trace width = 5 mils
･Trace width = 7 mils
･Differential trace spacing = 6 mils
･Differential trace spacing = 5 mils
･2 signal layers
･No via required on module PCB
･Layer connection = layer 2 (near top)
･Counterbored (18mil stub)
･2 via (connector side and Device side)
10/12
4inch Host, Driven from Host Side
CFP2 CFP4 Channel SI Performance
Simulation Result
Insertion Loss (Sdd21)
(dB)
7inch Host, Driven from Host Side
4inch Host, Driven from Module Side
7inch Host, Driven from Module Side
Return Loss (Sdd11)
(dB)
-4.5 dB
-19.0 dB
-9.5 dB
-9.0dB
-7.2 dB
-13.0 dB
(dB)
14G
28G
14G
Near-end Cross-talk of Top side
(dB)
28G
Far-end Cross-talk of Top side
-34 dB
-39 dB
-40 dB
-43 dB
14G
28G
14G
28G
11/12
Summary
• IEEE 802.3bj should adopt both QSFP28 and CFP4 as
baseline proposal for MDI
12/12