Inputs
Combinational
circuit
Outputs
Memory
elements
Fig. 5-1 Block Diagram of Sequential Circuit
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Inputs
Outputs
Combinational
circuit
Flip-flops
Clock pulses
(a) Block diagram
(b) Timing diagram of clock pulses
Fig. 5-2 Synchronous Clocked Sequential Circuit
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
1
0
R (reset)
Q
1
0
Q⬘
S (set)
(a) Logic diagram
S
1
0
0
0
1
R
0
0
1
0
1
Q⬘
0
0 (after S ⫽ 1, R ⫽ 0)
1
1 (after S ⫽ 0, R ⫽ 1)
0
(b) Function table
Fig. 5-3 SR Latch with NOR Gates
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Q
1
1
0
0
0
1
0
S (set)
Q
1
0
Q⬘
R (reset)
(a) Logic diagram
S R
Q Q⬘
1
1
0
1
0
0
0
1
1
1
0
1
1
1
0
(b) Function table
Fig. 5-4 SR Latch with NAND Gates
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
1
1 (after S ⫽ 1, R ⫽ 0)
0
0 (after S ⫽ 0, R ⫽ 1)
1
S
Q
C
Q⬘
C S
0
1
1
1
1
R
X X
0 0
0 1
1 0
1 1
Next state of Q
No change
No change
Q ⫽ 0; Reset state
Q ⫽ 1; set state
Indeterminate
R
(a) Logic diagram
Fig. 5-5 SR Latch with Control Input
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
(b) Function table
D
Q
C D
C
Q⬘
(a) Logic diagram
Fig. 5-6 D Latch
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
0 X
1 0
1 1
Next state of Q
No change
Q ⫽ 0; Reset state
Q ⫽ 1; Set state
(b) Function table
S
S
D
R
R
C
SR
SR
Fig. 5-7 Graphic Symbols for Latches
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
D
(a) Response to positive level
(b) Positive-edge response
(c) Negative-edge response
Fig. 5-8 Clock Response in Latch and Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
D
D
C
Y
D latch
(master)
D
C
CLK
Fig. 5-9 Master-Slave D Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
D latch
(slave)
Q
S
Q
CLK
R
Q⬘
D
Fig. 5-10 D-Type Positive-Edge-Triggered Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
D
D
C
(a) Positive-edge
C
(a) Negative-edge
Fig. 5-11 Graphic Symbol for Edge-Triggered D Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
J
D
Q
J
C
K
CLK
C
(a) Circuit diagram
Fig. 5-12 JK Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Q⬘
K
(b) Graphic symbol
T
T
J
T
D
C
C
K
C
(a) From JK flip-flop
(b) From D flip-flop
Fig. 5-13 T Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
(c) Graphic symbol
S
Q
CLK
R
Q⬘
D
Reset
(a) Circuit diagram
Data
CLK
D
C
R
Q
Q⬘
R C D Q Q⬘
0 X X 0 1
1 ↑ 0 0 1
1 ↑ 1 1 0
Reset
(b) Function table
(b) Graphic symbol
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 5-14 D Flip-Flop with Asynchronous Reset
x
D
A
C
A⬘
D
B
C
B⬘
CLK
y
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 5-15 Example of Sequential Circuit
0/0
1/0
0/1
00
1/0
10
0/1
01
0/1
1/0
1/0
11
Fig. 5-16 State Diagram of the Circuit of Fig. 5-15
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Present
Next
state Inputs state
x
A
D
y
C
CLK
x
0
0
1
1
0
0
1
1
y
0
1
0
1
0
1
0
1
A
0
1
1
0
1
0
0
1
(b) State table
(a) Circuit diagram
01, 10
00, 11
0
00, 11
1
01, 10
(c) State diagram
Fig. 5-17 Sequential Circuit with D Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
A
0
0
0
0
1
1
1
1
A
J
C
x
K
J
B
C
K
CLK
Fig. 5-18 Sequential Circuit with JK Flip-Flop
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
1
1
0
00
0
11
0
01
0
10
1
1
Fig. 5-19 State Diagram of the Circuit of Fig. 5-18
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
x
A
T
y
C
R
0
T
B
C
R
0
1
00/0
1
1
1
11/1
CLK Reset
(a) Circuit diagram
Fig. 5-20 Sequential Circuit with T Flip-Flops
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
01/0
10/0
0
(b) State diagram
0
0ns
10ns
20ns
30ns
40ns
50ns
60ns
testTcircuit.x
testTcircuit.CLK
testTcircuit.RST
testTcircuit.y
testcircuit.A
testcircuit.B
Fig. 5-21 Simulation Output of HDL Example 5-7
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
70ns
80ns
90ns
0/0
0/0
a
0/0
1/0
0/0
0/0
b
c
1/0
1/0
g
0/0
d
1/1
0/0
1/1
1/1
f
1/1
Fig. 5-22 State Diagram
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
e
0/0
0/0
a
0/0
1/0
e
0/0
0/0
b
c
1/0
1/1
d
1/0
1/1
Fig. 5-23 Reduced State Diagram
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
0
0
S 0 /0
0
S 3/1
1
0
1
S 1/0
1
S 2/0
1
Fig. 5-24 State Diagram for Sequence Detector
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Bx
00
B
11
01
10
A
0
A
1
1
1
1
1
1
1
1
x
DA Ax Bx
DB Ax Bx
Fig. 5-25 Maps for Sequence Detector
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
y AB
1
D
A
C
x
D
B
C
B⬘
CLK
y
Fig. 5-26 Logic Diagram of Sequence Detector
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Bx
00
B
11
01
10
1
0
1
X
Bx
00
X
X
X
0
A
11
10
X
X
X
X
0
1
1
1
x
x
J A Bx
K A Bx
B
01
11
10
1
X
X
A
A
01
A
A
A
B
Bx
00
A
B
Bx
00
01
X
X
X
X
1
X
X
A
1
JB x
1
x
K B (A 丣 x)
Fig. 5-27 Maps for J and K Input Equations
10
1
0
x
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
11
x
A
J
C
K
A⬘
J
B
C
K
CLK
Fig. 5-28 Logic Diagram for Sequential Circuit with JK Flip-Flops
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
B⬘
000
001
111
010
110
011
101
100
Fig. 5-29 State Diagram of 3-Bit Binary Counter
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
A1
A2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A0
T A2 A 1 A 0
T A1 A 0
Fig. 5-30 Maps for 3-Bit Binary Counter
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
T A0 1
A2
C
T
A1
C
T
A0
C
T
CLK
1
Fig. 5-31 Logic Diagram of 3-Bit Binary Counter
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
x
S
Full
adder
y
C
Q
D
CK
Fig. P5-7
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
A⬘
A
C
B⬘
B
C
T
T
CLK
Fig. P5-8
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
0/0
001
0/0
1/1
1/0
100
011
1/1
0/0
0/0
1/1
010
1/1
000
Fig. P5-19
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
0/0