E0-286 "VLSI Test“
Fault models and ATPG:
Logic fault models: SAF, TDF, PDF, Iddq, St-BDG, Dy-BDG,
SDD, etc. Basics of test generation and fault simulation.
Combinational circuits. Sequential circuits.
Specific algorithmic approaches. Illustrative examples. CAD
framework. Optimisations.
Why DFT
q Enhanced observability and controllability.
q Results in easier fault detection as well as coverage improvement (often along the non-functional
non
path).
q Reduces ATPG complexity and ATPG tool run--times.
q Simplifies design too. Common goals driven by partitioning, power, I/Os, etc.
q Simplifies tester environment. On-chip
chip BIST versus external tester resources.
q Ease of debug and diagnosis.
q Test time reduction.
q Examples: Scan design. I/O bounding. Test modes for clock selection, pin-muxing.
pin
Scan
compression – shorter chains. Design partitioning – easier routing of controls. Several TI-IPs
(Test Infrastructure IPs), e.g. BIST controllers, etc.
Examples of DFT
q IP and SOC test and integration:
¦ Various test modes and related controls.
¦ To enable DFT / enable intra-IP and interIP test.
q For low power test:
¦ Test of DUT: ATPG fill or scan
partitioning techniques.
¦ Test of PM. Test with PM.
q Test wrappers:
¦ Bounding controls. Inter-IP and intra-IP
controls. ExTest and InTest modes.
q For ATPG:
¦ Scan and clock controls.
q For online test:
¦ Memory ECC.
¦ Normal mode / test mode concurrency.
¦ Self-test.
¦ Logic ECC. What are valid / invalid
opcodes / operands (code-words)?
¦ Mapping of CW -> CW / NCW in
absence / presence of faults.
q For TTR:
¦ Higher multi-site. Reduced pin-count test.
¦ Self-test.
q For reliability / yield:
¦ Monitors. Margins.. Calibrators.
Redundancy.
q Test interfaces:
¦ JTAG, 1500.
Defects, Faults and Errors
Defects, faults and errors:
q Defects must results in faults. Faults must result in observable errors. Test depends upon
observable errors.
q Margins help tolerate (marginal) defects. No resulting faults. Approximate tests can now detect
gross defects. Examples: Transition fault ATPG (no delay measurement). Structural tests for
analog / RF circuits (no performance measurement).
q Non-maskable faults must be detected or tolerated.
Single fault considered during ATPG. Multiple faults occur in DUT. No coverage lost.
q All MFs detected if all SFs are detected (across all patterns) and if no one fault impacts another.
q A fault must be detected before another one occurs, i.e. two faults must not occur faster than the
test application time for all faults.
q Redundant logic can cause failure of irredundant logic.
Examples
A
Single fault and multiple faults.
A
B
Z
A/1
Multiple faults
1
0
0
0
0
-> B/0
0
1
0
1
0
-> Z/1
1
1
1
1
1
S1
S2
Z
0
0
I1
0
1
I2
1
0
I3
1
1
I4
Z
Redundant logic affecting non-redundant logic. B
I1
I2
I3
I4
Z
I1
S1
S1
S2
S2
Coupling
Unused, But I1 forced to 1
Redundant Logic
q Structurally redundant logic in Consensus theorem not covered with any input.
q Unused logic in 3-1 mux not covered with functional inputs.
q Unoptimised set of minterms require additional non-functional
non
inputs. Practically very relevant.
A
S
OR
Z = A.S + B.S’ + A.B
B
S’
A
B
X
never tested
AB
S
00
01
11
10
0
0
1
1
0
1
0
0
1
1
Fault Models and Fault Sizes
# Nets
# Gates
# Transistors
# Paths
Slack paths
N
G=N
5*G
(N / 10) / 1000
N*3
FM
Single faults
Multiple faults
SAF
TDF
PDF
SDD
SBF
DBF
TGF / Pseudo SAF / Iddq
Functional
2*N
2*N
2*P
2*N*3
N*(N-1) / 2 * (4-2)
N*(N-1) / 2 * (16-4)
2*N
Unbounded
2, 3, …, N at a time
2, 3, …, N at a time
2, 3, …, N at a time
Unbounded
Total
Fault List Pruning
q Equivalent faults.
q Fault dominance.
q Fault class dominance. SAF w.r.t.. others. SAF coverage is effective, though not sufficient.
q Examples.
c
a
b
d
Equivalent
Dominant
a
b
Y
Either
b
c
N
b over c
b
d
N
b over d
c
d
N
N
Other faults
TDF – Dominated
SAF - Dominant
Additional Faults in Memories – Example of what is Different from Logic
Neighbourhood Pattern Sensitive Faults (NPSFs):
q Interaction with upto 8 neighbouring bits
q For each centre bit, there are 8 Distance 1 neighbours
and 16 Distance 2 neighbours.
q Number of distance N neighbours in a square tile =
[(2*N
[(2*N-1)^2
- (2*N+1)^2] = 8*N.
q Fault primitive (FP): <S/F/R>
q Different topologies drive tile formation and test
¦ S: sensitizing operation (w0, w1, r0, r1….) sequences.
¦ F: faulty behaviour (0, 1, , )
q Exponential complexity of March algorithms for small N.
¦ R: read result, if read operation is present
q Example:
< r1 / ? / 0 > =
S : r1 -> read - expected 1
F : ? -> cell flips to 0
R : 0 -> read - obtained 0
Successive R/W operations:
q To stress the bit-lines
bit
and sense amplifiers.
Both these require non-functional
non
test patterns.
Conventional CPU code will fail to catch them.
Why Stuck-at Fault Model?
q SA0 / SA1 fault from bipolar IC legacy. “Short” is 0,1. “Open / Floating” is 1.
1
q CMOS has stuck-short / stuck-open
open faults. The latter requires a two-pattern
two
test. One to initialize
a node and the other to set it too opposite value.
q Similar test required for memory and tristate o/p buffer.
buffer
Has forced introduction to sequential ATPG., besides use of non-scan flip-flops.
Examples: Memory operations, tristate buffer output setting (fault detection). Two (Multiple) pattern
tests with observe for each / last.
I1
E1
A
E1
C
Output
I2
B
E2
E2
10
Inputs and States
PIs
POs
Combinational circuit:
q Number of possible input combinations for a
combinational circuit is 2^(#PI).
Combinational
q Number of possible output combinations <= Number of
possible input combinations.
Present
State
Next
State
q No fixed relationship between functional specification
and test patterns: #PI and #PO. Number of specified
combinations out of 2^(#PI) and 2^(#PO).
Sequential circuit:
q States complicate this process further.
q More possible input combinations: 2^(#PI + #PS).
q Each PS may require cycling through many PI+NS
combinations.
q Handled by unrolling different sequential frames into
consecutive combinational frames.
q NS and PS faults must be observed only on POs.
11
Complexity of Test Generation
q For I inputs, 2I combinations. For I = 100, TT = 10 15 years @ 30 MHz. (???)
q For I inputs and S state bits, 2(I+S) combinations. For each S, many sequences of I needed. For I
= 100 and S = 106, TT = ???. With scan, combinations are same. TT is proportional to S*2I .
q For 106 flip-flops and 105 patterns, # shift cycles in simulation is 1011. @ 1000 cycles per second,
this is 108 seconds or 3 years. With scan integrity check, shift time is 0 ms.
q Scan shift time for 106 flip-flops and 105 patterns @ 30 MHz is 3000 s (50 minutes).
q With scan compression:
¦ For compression ratio of 100, this time is 30 s.
¦ Lesser time for state setting.
¦ More ATPG complexity. Only 1 / 100 ffs can be set uniquely.
q Additional complexity since back-tracking,
tracking, multiple path sensitization and forward tracking
(propagation) are required.
12
Schneider’s Circuit
Illustration for:
q Forward propagation (D drive) and backward justification.
q Multiple path sensitisation.
q Non-optimal and optimal pattern sets. Non-unique
unique pattern sets.
13
ATPG Topics
D-algebra:
q What is need for multi-valued
valued logic representation for ATPG?
q Examples to illustrate “D frontier”.
q Simplification provided by PODEM, FAN and other test generation algorithms.
q Iterative model of sequential circuit for test generation. D propagation across frames.
Flow for test generation:
q Fault simulation: Need and methods.
q Fault list management.
q Fault classification (detectable / undetectable / tested / untested).
q Pattern compaction: Static and dynamic.
q Using don’t care bits.
Questions: Optimised logic => Sometimes more patterns? Larger circuits => More don’t care bits?
Larger circuits => Lesser entropy?
14
Bounds
q 2-1 Mux:: No redundancy. 6 / 8 patterns are sufficient. Both inputs identical render the select
input redundant. (00 / 11 input patterns are not required).
q ExOr gate: No redundancy.
¦ All 4 / 4 patterns required for internal faults.
¦ 3 / 4 patterns adequate for I/O faults.
q Adder: No redundancy. Finite number of patterns required. Lower bound = 4, independent of the
data width of the adder.
q Decoder: No redundancy. Finite number of patterns required. Upper bound = 2I for an I input
decoder. For a 32K word memory, 32K addresses are required to test it (for one iteration –
March sequence).
q Diagrams.
15
Testing I/Os versus Internal Nets
Testing I/Os is not same as testing internal nets. Few examples below.
q ExOr :
¦ 3 patterns for black-box.
¦ 4 patterns for internal circuit.
q CPU Address / Data:
¦ Few patterns (<10) can check all SAFs on these I/Os.
¦ Practically 1000s of patterns required.
q Counter :
¦ Value change in state bits versus navigation from one state to another.
16
Test Logic Is Good / Bad
q DFT+ BIST / DUT:
¦ Bad / Bad è Bad.
¦ Good / Bad è Bad.
¦ Bad / Good è Bad.
¦ Good / Good è Good.
q Probable defect in DFT + BIST logic is acceptable. Discard the device. Systematic defect is not.
q In comparison, the tester is never faulty.
17
Scan Implementation
From other
FF(Q)
SI1
From other
FF(Q)
From other
FF(Q)
SO2
D
Q
SD FF1
FF6
To other
FF(D)
SE
From other
FF(Q)
FF2
FF5
FF3
FF4
SI2
SO1
To other
FF(D)
Exclusive Scan path
Functional path
Cycles
1
2
3
4
5
6
7
SI1
SI2
SE
SO1
SO2
18
Scan Implementation (2)
q SE can be shared between two scan chains if they are running in tandem, or can be dedicated if
they are running independently.
q Shift-out
out for Pattern P1 happens in parallel with shift-in
shift for Pattern P2.
q Cycles1,2,3,5,6,7:
¦ SI1->FF1(SD)->FF1(Q)->FF2(SD)->FF2(Q)
>FF2(Q)->FF3(SD)->FF3(Q)->SO1.
¦ SI2->FF4(SD)->FF4(Q)->FF5(SD)->FF5(Q)
>FF5(Q)->FF6(SD)->FF6(Q)->SO2.
q End of Cycle 3: End of shift-in.
in. Pattern from FFs(Q) applied to logic.
q End of Cycle 4: Response captured into FFs(D). Start of shift-out.
shift
19
Various Aspects of Scan
Design aspects:
q Types of scan flip-flops.
q Inputs / Outputs and controls required.
q Number of scan chains and lengths.
q Order of stitching flip-flops into scan chains.
q Stitching across IPs / Domains.
q Full scan versus partial scan.
Scan: Changes state setting complexity from exponential to linear.
q Ease of controllability. Ease of observability.
q No need for scan shift simulations after scan integrity checks.
q At-speed
speed next state generation possible without tester inputs.
20
Scan Compression
From Tester
CoDec
DECOMPRESSOR
SPREADING NETWORK
DUT
CoDec
• Several don’t care bits in every scan pattern.
• More of them for the latter patterns.
è Scope for compression.
Two aspects:
• Few external channel (from tester) connected
to many internal scan chains.
• Long chains converted to shorter chains.
SPACE COMPACTOR
SEQUENTIAL COMPACTOR
To Tester
21
Scan Compression Targets and Bounds
q Total number of care bits required to test a circuit fully (near constant) è Circuit entropy.
q Entropy drives upper bound on compression. Typical number 100.
q Compression limited by entropy. Can only be increased through coverage loss. (Concurrency is
independent of compression).
q Care-bits
bits must be encoded by ATPG tool to be correctly decoded by decompressor.
q DUT response compressed in compactor. Xs hamper this compression. X-handling
X
hampers
encoding.
q TDV compression is the first measure.
¦ TAT compression depends upon number of tester and DUT channels, and tester handshake
mechanisms.
¦ Often controlled outside the CoDec architecture.
¦ But TAT is often more important.
22
Functional and Structural Tests
q Ubiquitous need for non-functional inputs:
¦ Examples: Memory back-to-back
back reads / writes, tristate two pattern sequential test, EXOR
gate, structural redundancy in synthesised logic (non-minimal
(non
set of minterms), functional
redundancy in 3-1 mux,, counter with unused states, etc.
¦ Iddq: Non-functional
functional inputs are also required for transistor defects, e.g. 00 input to two-input
two
NAND gate.
q Scan state itself is not functional:
¦ Next state after scan shift is not necessarily functional. It is just reachable.
¦ Launch-off capture and launch-off
off shift patterns can both have non-functional
non
launch states.
¦ Path delay pattern: Just a valid transition, not necessarily a valid path.
q Memory RAM sequential patterns have several scan operations per pattern (five below):
¦ Scan Address2 => Write Data2 (initialize).
¦ Scan Address1 => Write Data1.
¦ Scan Address2 => Read Data2. (Detects faults where A1 maps incorrectly to A2).
23
Iddq Current Test
Inverter:
q Input A toggles from 0 -> 1: Output Q changes from 1 -> 0.
Current spike between quiescent values.
q What is an acceptable steady state value? Is it a range?
Embedded NAND gate:
q Iddq patterns generated based on toggle /pseudo-stuck-at
/pseudo
fault model.
q Either nets toggle, or toggle effect is seen at gate output. No
need to propagate the fault to a primary output.
q Iddq current expected to be different between fault-free
fault
and
faulty conditions.
q New input combinations may be required / used, e.g. 00,
depending upon model used for ATPG.
24
Iddq Threshold
Four quadrants:
q Device vs Iddq:
¦ Good / Low.
¦ Good / High.
¦ Bad / Low.
¦ Bad / High.
q Yield recovery in the middle two
cases through setting appropriate
thresholds and outlier analysis.
25
Waveforms for Different Patterns
shift_in
capture
shift_out
Combinational ATPG / SAF pattern.
shift_in
no capture
shift_out
Iddq, TGF pattern.
shift_in
Multiple captures shift_out
Sequential ATPG / TRF pattern.
26
Example
Assume a transition fault ATPG test in Foil 18:
q FF1(Q): 1 -> 0.
q FF2(Q): 1 -> 0.
q Response captured in FF4(D).
Cycles
Shift1
Shift2
Shift3/Init
Launch
Capture
Shift …
FF1(Q)
FF2(Q)
FF4(D)
27
At-speed ATPG Tests
Two pattern tests: V1 -> V2. V1 is initialisation pattern. V2 is launch pattern.
q Launch condition enabled through scan initialisation (non-functional).
q Next state after scan shift is not necessarily functional. Depends on synthesis of next state
functional. Very likely only reachable for incompletely state machines.
q Reachable ? Functional. Former depends upon synthesis. Latter depends upon specification.
For a completely specified machine, the two are same.
q Launch-off capture and launch-off
off shift patterns can both have non-functional
non
launch states.
28
Two Pattern Tests
q Three methods for launch (V2), after initialization (V1):
¦ V2 is shifted value of V1 (combinational). Different V2 for all V1 guaranteed.
¦ V2 is functional state of V1 (sequential). Different V2 for all V1 not guaranteed.
¦ V2 is functional state of V1 after many cycles. Higher chance of V2 being different from V1.
¦ V2 and V1 are independent (two sets of scan flip-flops
flip
– enhanced scan chain).
launch
capture
shift_in (LOS)
shift_out
shift_in (LOC)
V1
V2
scan_enable
Launch off capture
scan_enable
Launch off shift
Enhanced SC
Orig. SC
29
Desirable Transitions
q Transition fault pattern does not necessarily cause a transition in the capture flip-flop.
flip
¦ 0->1
>1 transition on S is a valid transition fault test for A = 1 and B =1->0.
=1
¦ Fault-free output does not change: 1->1.
>1. Faulty o/p: 1 -> 0.
q Path delay pattern: A transition in capture flip-flop
flop is guaranteed. However, not necessarily
through a valid path.
q Path delay tests can be robust (single launch transition), non-robust
non
(other enabling launch
transitions), functional sensitisable (other enabling paths). Considerations for multi-cycle
multi
paths
and false paths.
q Multiple cycle launches may be required to achieve a functional launch state.
A
S
Z = A.S + B.S’
B
S’
30
Small Delay Defects
Earlier metric:
New metric:
•
10
5
0
# transition faults detected
4
8
12
16
20
24
28
32
36
40
44
# transition faults detected.
Nodes
•
Slack
weighted as:
•
(Fault * Minimal slack) / (Slack
along detected path)
•
Coverage
Pattern count
Area under the slack curve.
q Take all patterns for a given
slack – accept coverage
obtained.
q Take all patterns for a given
coverage – accept slack used.
10%
20%
30%
40%
50%
% of detection path slack w.r.t.
minimum path slack
60%
10%
20%
30%
40%
50%
% of detection path slack w.r.t.
minimum path slack
60%
31
Defect Oriented Testing
Inductive fault analysis: Artwork of faults.
Parameters:
q (x,y) co-ordinates.
q Radius and area.
q Probabilistic distribution considered for number of defects.
32
Assignments
A.
1.
2.
3.
4.
Assume SA0 and SA1 faults on all nets:
Generate an optimal pattern set for Schneider’s circuit on Foil 13.
Generate an optimal pattern set for the tristate buffer circuits on Foil 10.
Generate an optimal pattern set for a full adder circuit with two inputs of two bits each.
Generate an optimal pattern set for a three bit binary counter using D flip-flops
flip
with states as
outputs (with reset state of all 0s). For the same circuit, generate an optimal pattern set with
only an over-flow
flow output, which is set when the state flip-flops
flip
are all1s.
B.
1.
2.
3.
Assume S-R and S-F faults on all nets:
Generate an optimal pattern set for the tristate buffer circuits on Foil 10.
Generate an optimal pattern set for the three bit binary counter in A(4) for both the cases.
Consider the case where this binary counter iis used only for five states, i.e. overflow is
generated for state 101.
33
Backup
34