Department of Electrical Engineering, College of Engineering, University of North Texas, Denton Digital Logic Design (EENG‐2710) Homework‐ 4 (Spring 2016) Facilitator: Dr. Partha Guturu Learner: DUE DATE: April 19, 2016 (Tuesday) Maximum Marks: 50 The total marks (50) given here will be scaled down for the final grading. This homework is mainly for your practice. You may consult your friends for solving the problems or verification of answers, but please do not simply do blind copying and submit. It is in your own interests that you make an effort to solve the problems because they help you to do well in the final examination to be held on the following Thursday with questions similar to those on this homework. In case you are not getting any help, you better come to my office at B‐235 early on (not the day before deadline) and discuss your problems. Q. 1. (a) From the excitation equation of an SR latch derived from the truth table mapping of S, R, and Qt values
onto Qt+1 values, show how the latch can be implemented using only NAND gates. Also, show an equivalent
implementation using only NOR gates. Discuss why the two NAND (or NOR) outputs correspond to Q and
Q for any valid combination of SR inputs. Indicate the problem when SR=11 is allowed.
(2 + 1 + 1 + 1 + 1= 6 Marks)
(b) Starting with the truth table for gated SR latch, derive its excitation equation, and then show how an SR
latch can be converted into an SR flipflop (gated SR-Latch)
(5 Marks)
(c) Derive the excitation equations for the D and JK flopflops, and then by tallying the excitation equations,
convert a D flipflop into a JK-flipflop. Draw the circuit diagram.
(4 Marks)
(d) What is a racing condition? Discuss briefly the two flipflop solutions to avoid racing conditions.
(2 Marks)
Q. 2. (a) Draw the state diagrams of the up and down BCD counters.
(1 Mark)
(b) With the help of a diagram, explain the ad hoc design (using JK-flipflops) of a BCD counter that could be used
in both count-up and count-down modes.
(4 Marks)
Q. 3. Draw the diagram of a 4-bit shift register using D-flip-flops and with the controls for parallel input, left shift
and right shift. If none of the controls is activated, the shift-register will save its current state, when the next clock
pulse comes in. Provide a brief explanation of how the device works.
(5 Marks)
Q.4. Reduce the state-table on the right hand side to a minimal
equivalent table by using the equivalent partitions method.
(3 Marks) Hint: Reduced machine will have 4 states. Q. 5. A circuit must detect a 01 sequence. The sequence sets z = 1,
which is reset only by a 00 sequence. For all other cases, z = 0.
Overlap is allowed in the sense that the second bit of the reset
sequence “00” can be counted as the first bit of the next set
sequence “01.” For example, for input sequence x as follows, the
corresponding output sequence z would be:
x = 010100100
z = 011110110
For this circuit:
Input x 
PS (Present State)
NS (Next State),Z
(Output)
x=0
x=1
A
D, 1
G, 1
B
C, 0
D, 1
C
E, 0
F, 1
D
F, 1
B, 1
E
B, 0
F, 1
F
D, 1
C, 1
G
A, 0
D, 1
(a) Develop state diagram with 5 states with state S0 representing the initial state or the state in
which even the first bit of the set sequence “01” is not detected, and states S1, S2, S3, and S4
representing the states of recognition of, respectively, the first bit and the second bit of the set
sequence “01”, and the fist and second bits of the reset sequence “00.”
(2 Marks)
(b) Minimize the number of states required using the partitioning method (minimal machine will have 4
states)
(2 Marks)
(c) Use the JK flopflops to implement the circuit (2 flipflop are enough). Assign Q1Q0= 00 to state A,
Q1Q0= 01, 10, and 11 to the states considered in their alphabetical order. Present the state table by
(2 Marks)
representing the states in terms of the Q1Q0 values.
(d) From the output transition table for JK flipflops, obtain the table showing for each state and input
combination, the required J and K values that will cause the transitions shown in the table in 3(c).
(5 Marks)
(e) Design using Karnaugh maps the 4 combinational circuits required to feed into the inputs of the 2 JK
flipflops. Draw the final circuit (including function for z) for the sequence detection.
(4 + 5= 9 Marks)