CSCE 3953 System Synthesis and Modeling
Lecture 3 Review of Sequential
Logic Design
Instructor: Dr. Jia Di
Sequential Logic Definition
ƒ Outputs depend on the history of the applied
inputs as well as on their present value
ƒ Timing is important
ƒ Memory elements exist
ƒ Delay can be involved
ƒ Synchronous, deterministic sequential machines
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Storage Element – Latches
Level-sensitive
3
Storage Element – Flip-Flops
D-type Flip-Flop
Transmission Gate
4
Storage Element – Flip-Flops
D-type Flip-Flop
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Storage Element – Flip-Flops
J-K Flip-Flop
T Flip-Flop
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Busses and Three-State Devices
ƒ Busses are multi-wire signal paths that connect
multiple functional units in a system
ƒ Some units are bus drivers/masters; some are
receivers/slaves; some can be both
ƒ Reduced space compared to dedicated signal
paths (crossbars)
ƒ Need to guarantee only one driver/master can
drive the bus at a time
ƒ Other bus drivers/masters need to set their
outputs to high-impedance states
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Busses and Three-State Devices
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Busses and Three-State Devices
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Design of Sequential
Machines
Sequential Machines
ƒ Finite state machine (FSM)
ƒ The future behavior is completely characterized by its
input and its present state
ƒ “Brain” of a digital system
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FSM Synchronization
ƒ Memory elements are triggered by clock edges
ƒ Overcome race issues
™ Ensure setup and hold time are satisfied at FFs
™ Ensure clock skew does not compromise the synchronicity
™ Provide synchronizers at the asynchronous inputs
ƒ Clock can be either symmetric or asymmetric
ƒ Clock period needs to be long enough
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Mealy Machine and Moore Machine
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Six-step Process
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
1.
2.
3.
4.
5.
6.
Understand the statement of the Specification
Obtain an abstract specification of the FSM
Perform a state minimization
Perform state assignment
Choose FF types to implement FSM state register
Implement the FSM
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Example – Vending Machine
ƒ General Machine Concept
Deliver package of gum after 15 cents deposited
Single coin slot for dimes and nickels
No change
ƒ Step 1: understanding the problem (draw a
picture!)
N
Coin
Sensor
D
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechanism
Clk
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Example – Vending Machine
ƒ Step 2: Map into more suitable abstract representation
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Draw state diagram:
inputs: N, D, reset
S3
output: open
N
Reset
S0
N
S1
N
D
D
S2
N
D
S4
S5
S6
[open]
[open]
[open]
D
S7
S8
[open]
[open]
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Example – Vending Machine
ƒ Step 3: State Minimization
Present
State
Reset
0¢
0¢
N
reuse states
whenever
possible
5¢
D
5¢
N
10¢
D
10¢
N, D
15¢
[open]
15¢
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
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Example – Vending Machine
ƒ Step 4:
State
Encoding
Present State Inputs
D N
Q1 Q0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
Output
Open
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
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Example – Vending Machine
ƒ Step 5: Choose FFs for Implementation
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
Q1
D
Q0
N
D1 D Q
CLK
R
Q1
Q \ Q1
\reset
N
\ Q0
Q0
\N
Q1
N
Q1
D
OPEN
D0 D Q
CLK
R
Q0
Q \ Q0
\reset
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Moore and Mealy Machines
State Diagram Equivalents
(N D + Reset)/0
Reset/0
N D + Reset
Reset
0¢
0¢
[0]
Reset/0
Mealy
Machine
Reset
N/0
5¢
N D/0
Moore
Machine
N
5¢
D/0
ND
D
[0]
N
N/0
10¢
10¢
D
D/1
N D/0
N+D/1
15¢
[0]
N+D
15¢
Reset/1
[1]
ND
Outputs are associated
with States
Reset
Outputs are associated
with Transitions
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FSM Design Example – BCD to
Excess-3 Code Converter
ƒ Excess-3 code word is obtained by adding 310 to the decimal value of
the BCD word and taking the binary equivalent of the result
ƒ Serial input bit stream
ƒ Mealy machine design
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FSM Design Example – BCD to
Excess-3 Code Converter
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FSM Design Example – BCD to
Excess-3 Code Converter
State transition graph (STG)
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FSM Design Example – BCD to
Excess-3 Code Converter
State transition table with state assignment
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FSM Design Example – BCD to
Excess-3 Code Converter
Variable logic expression derivation
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FSM Design Example – BCD to
Excess-3 Code Converter
Mapped circuit
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