CS221 Di it l D i
CS221: Digital Design
Clocked R‐S, D, J‐K and T Flip‐
Flop Dr. A. Sahu
Dept of Comp. Sc. & Engg.
Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
Out e
Outline
• Design a new building block, a flip‐flop, that stores one bit
bi
• Latch Vs Flip Flop • Master Slave Flip‐Flop
D Flip‐Flop
Flop, JJ‐K
K Flip
Flip‐Flop
Flop and T Flip
and T Flip‐Flop
Flop
• D Flip
• Combine that block to build multi‐bit storage – a register
a register
Sequential Circuit
Sequential Circuit
x
b
Input
Combinational
logic
n1
output
n0
s1
clk
s0
History/
S
Sequence/State
/St t
Y (t) = F (a(t),b(t), H)
H is History/Sequence/State
H is History/Sequence/State
Where to Store this History (Memory Element)
Bit Storage Using an SR Latch
SR latch
S (set)
• Does the circuit to the right, with cross‐
p
g
,
coupled NOR gates, do what we want?
– Yes! How did someone come up with that circuit? Maybe just trial and error, a bit of insight...
S=0
0
1
R=1
1
0
R1
0
t 1
0
Q1
0
S
t
1
0 Q
S=0
0
1
R=0
t
1
0 Q
S=1
1
0
R=0
Q
R (reset)
S=0
t
0
1 Q
t
1
0
0
1 Q
R=0
Problem with SR Latch: Race Condition
• Problem: If S=1 & R=1 simultaneously and both released to 0, we don’t know what value Q will 1
S
S=1 take
S=0
S=0
t
t
t
0
0
0
R=1
0
0
0
0 Q
1
1
1
1 Q
R=0
R=0
0
0 Q
1
R
0
1
t
0
1
Q
0
Q may oscillate. Then, because one path will be slightly longer than the other, Q will eventually settle to 1 or 0 – but we don
0 but we don’tt know which.
know which
t
Q
1
0
1
0
Problem with SR Latch
• Problem not just one of a user pressing two buttons at same time
• Can also occur even if SR inputs come from a circuit that supposedly never sets S=1 and R=1 at same time
does due to different delays of different paths
– But
But does, due to different delays of different paths
X
Arbitrary
circuit
S
SR latch
1
X
0
1
Y
0
Q
Y
R
1
S
0
SR = 11
The longer path from X to R than to S The longer path from X to R than to S
causes SR=11 for short time – could be long enough to cause oscillation
1
R
0
Solution: Level‐Sensitive
Solution: Level
Sensitive SR Latch
SR Latch
• Add enable input “C” as shown
– Only
Only let S and R change when C
let S and R change when C=0
0
• Ensure circuit in front of SR never sets SR=11, except briefly due to path delays
– Change C to 1 only after sufficient time for S and R to be stable
Ch
C t 1 l ft
ffi i t ti
f S d R t b t bl
– When C becomes 1, the stable S and R value passes through the two AND gates to the SR latch’s S1 R1 inputs. Level-sensitive SR latch
S
S
S1
Q’
C
Q
R
C
Q
R
R1
Level-sensitive SR
latch symbol
Solution: Level‐Sensitive SR Latch
Level-sensitive SR latch
S
X
Clk
S1
C
Q
R
Y
S
1
Though SR=11 briefly...
0
1
R
0
C
1
0
a
1
S1
R1
R1
0
1
0
...S1R1 never = 11
Solution: Ensure, Stabilize, Store
Level-sensitive SR latch
S
X
Clk
S1
C
Q
R
R1
Y
Ensure
Stage
Never Happens SR=11
Stabilize Stage
Store Stage
When C=0 When
C=0
Stabilize SR and Use when C=1
Store bit
Clocks
• Clock period: time interval between pulses pulses
– Above signal: period = 20 ns
Freq
Period
• Clock cycle: one such time interval
100 GHz
0.01 ns
– Above signal shows 3.5 clock cycles
10 GHz
0.1 ns
1 GHz
1 ns
100 MH
MHz
10 ns
10 MHz
100 ns
• Clock frequency: 1/period
– Above
Above signal: frequency = 1 / 20 ns = 50 signal: frequency = 1 / 20 ns = 50
MHz
• 1 Hz = 1/s
Clock Signals for a Latch
• How do we know when it’s safe to set C=1?
d
k
h
’ f
– Most common solution –make C pulse up/down
– C=0: Safe to change X, Y C=1: Must not
C 0 Safe to change X Y C 1 Must not change X, Y
change X Y
– Clock signal ‐‐ Pulsing signal used to enable latches • Because it ticks like a clock
Because it ticks like a clock
– Sequential circuit whose storage components all use clock signals: synchronous circuit
Level-sensitive SR latch
S
S1
X
Clk
C
Q
R
Y
R1
Level‐Sensitive D Latch
• SR latch requires careful design to ensure SR=11 never occurs
ensure SR=11 never occurs
• D latch relieves designer of that burden
D latch
D
S
C
– Inserted inverter ensures R always opposite of S
Q
R
D
C
1
0
1
0
1
S
R
Q
D
Q’
C
Q
0
1
0
1
0
D latch symbol
Problem with Level‐Sensitive D Latch
• D latch still has problem (as does SR latch)
– When C=1, through how many latches will a signal travel?
– Depends on for how long C=1
D
d
f h l
C 1
• Clk_A ‐‐ signal may travel through multiple latches
• Clk_B ‐‐ signal may travel through fewer latches
– Hard to pick C that is just the right length
d
i k h i j
h i h l
h
• Can we design bit storage that only stores a value on the rising edge of a clock signal?
Y
D1
C1
Q1
D2
C2
Q2
D3
C3
Clk
Clk_A
Clk_B
Q3
D4
C4
rising edges
Q4
Clk
Flip Flop
Flip Flop
• Coin Flip : Head/Tail (1/0)
Coin Flip : Head/Tail (1/0)
• Latch have either one state 0 or 1
• Flip‐Flop (Both Master/Slave)
–Flip State/Flop State
Master ‐Slave D Flip‐Flop
••Flip
Flip‐‐flop: stores stores on clock edge, not level on clock edge, not level • Two latches, output of first goes to input of second, master latch has inverted clock signal
• So master loaded when C=0, then servant when C=1
• When C changes from 0 to 1, master disabled, servant loaded with When C changes from 0 to 1 master disabled servant loaded with
value that was at D just before C changed ‐‐ i.e., value at D during rising edge of C
D flip-flop
D latch
D
Dm
Qm
Clk
D latch
Ds
Qs’
Q’
D/Dm
Cm
Cm
master
Clk
Cs
Qs
servant
Q
Qm/Ds
Cs
Qs
Thanks