Special Tutorial
INTRODUCTION
TO THE ROLE OF REDUNDANCY
IN COMPUTER ARITHMETIC
D. E. Atkins
The University of Michigan
Introduction
Redundancy, the state of being in excess of what is
applied in the implementation of computer
arithmetic is motivated by three design goals: to improve
reliability, to increase speed of operation, and/or to provide
structural flexibility. In achieving the first goal, improvement of reliability, hardware redundancy and/or redundant
arithmetic codes are applied to the detection and correction
of faults. Although this is an increasingly vital area it will
not be discussed in this paper. Rather, the focus will be on
the other two potential benefits: more specifically, on the
judicious use of number systems employing redundancy in
representation. A positional number system with fixed
radix, r, is redundant if the allowable digit set includes
more than r distinct elements, thereby affording alternate
representations of a given numeric value. Uniqueness. of
representation is sacrificed with hope of greater gains. A
novel, rigorous treatment of redundant, radix polynomial
representation is included in Reference 1.
Although not central to the paper, it may be observed
that conventional floating point representations also
illustrate a form of representational redundancy in that, by
adjustments between the mantissa and characteristic, they
afford alternate representations of the same point on the
real number line. Normalization is used to reduce the
degree of redundancy.
The goals of this paper are (1) to review the realization
that the concept of representational redundancy relates
many of the arithmetic speed-up techniques previously
arrived at in a largely ad hoc manner; (2) to cite some of
necessary, as
the recent work which has been conducted in awareness of
this fact, and the theory which surrounds it; and (3) to
briefly review the properties of a particularly well studied,
redundant, signed-digit number system.
The tutorial nature of this presentation is motivated by
the author's belief that the maturity of the science of
computer arithmetic has not been sufficiently publicized
74
nor been adequately considered at the drawing boards of
mainframe manufacturers. An excellent, more introductory
tutorial, is found in Reference 2.
Redundancy to Accelerate Arithmetic
Multiplication
Redundancy in the Partial Product The use of carry-save
adders to accelerate the iterative portion of digital
multiplication is well-known. Its basis is the realization that
carries need not be propagated during each addition of a
long series of additions, provided that carries are explicitly
stored. Historically, carry-save adders have been designedby modification of conventional adders with propagating
carry. The carry and sum outputs, having weight 2 and 1,
respectively, may be interpreted as the digit values 0, 1, 2,
or 3. The radix or base remains at two, thus the carry-save
adder introduces redundancy into the representation of the
partial product. An alternate form of storing carries breaks
the carry chain differently and reduces the possible digit
values to 0, 1, or 2. This choice is preferable in that it
reduces the magnitude of truncation error resulting from
the loss of the least significant half of the product of a
floating point multiplication. Similarly, a propagating
borrow subtracter may be modified to create a borrow-save
subtracter which introduces the redundant digit set -2, -1,
0, 1.
The realization that the use of stored carries or borrows
was a way of introducing redundancy has lead to the
demonstration that the explicit identification of certain
digits as carries or borrows could be eliminated. Robertson3
has defined a deterministic procedure for the design of a
family of carry-borrow, adder/subtracters of which the
conventional structures are but one member. Rohatsh4 and
Borovec5 have elaborated on this work. Two particularly
practical cases are the "stored sign" adder and subtracter in
which the two outputs of a typical binary weighted
position are interpreted as a sign (+ or-) and a magnitude
COMPUTER
(0 to 1) giving rise to the symmetric redundant digit set,
-1, 0, +1. Note that the absence of the digit 2 further
reduces worst-case truncation error. An implementation
employing a stored sign subtracter is described in Reference
6.
Redundancy in the Multiplier Another acceleration
technique, typically used in conjunction with introducing
redundancy into the partial product, is that of recoding the
multiplier from a non-redundant to a redundant digit set.
This application of redundant representations was first
studied in conjunction with increasing the shift average-the
number of shifts, on the average, which may be expected
between successive additions. The recoding is designed to
increase the occurrence of strings of ones or zeros. The
benefits of recoding in this context rest upon the
assumption that bypassing the adder and/or use of multiple
shift paths is faster than passing through the adder, and that
the control is sufficiently asynchronous to take advantage
of the variable duration of the multiplication operation.
Although these assumptions are frequently not valid in
present day synchronous processors, technology has a way
of redefining what is best. Highly functional, modular
architectures motivated by LSI may well vindicate
asynchronous structures. References on multiplier recoding
include 7 and 8.
Redundant multiplier recodings are also effective in
enhancing higher-radix multiplication with either synchronous or asynchronous control. Binary multiplication is
performed at a higher radix by retiring more than one bit of
multiplier per iteration. In the absence of recoding, for
r times the
multiplication radix-r, multiples of 0, 1, 2,
multiplicand must be available. By recoding, redundancy
may be introduced into the multiplier in such a manner
that all the required multiples may be formed merely by
shifting and conditional negation. For example, Reference
6 describes a recoding which performs multiplication radix
7. The
256 using combinations of ±2i for i = 1, 2,
technique is based upon the replication of recoding
hardware which transforms the non-redundant, radix-4 digit
set 0, 1, 2, 3 into the redundant set -2, -1, 0, 1, 2. (See
Reference 9.)
...,
...,
Division
Redundancy in the Quotient To accelerate the
performance of division, redundancy may be introduced
into the representation of the quotient. The resulting
freedom of representation implies that comparisons
between the partial remainder and the divisor need not be
made to the full precision of the divisor. An outgrowth of
this observation is the so-called SRT division.10 In this
technique both the divisor and successive partial remainders
are normalized to the range Y2 to 1 by a process of left
shifts. After normalization, the divisor is either added to or
subtracted from the- shifted partial remainder depending
only upon a comparison of signs of the divisor and partial
remainder. The representation of the quotient is redundant
since each shift during normalization corresponds to a
quotient digit of 0, and the addition -and subtraction
correspond, respectively, to -1 and +1.
This division technique is, in effect, recoding the
quotient and thus, under the assumption that fast, multiple
shift paths are available, raises the question of what is the
shift average. A correspondence between multiplier and
quotient recodings has been formalized in Reference 11.
June 1975
The analysis is complicated by the fact that the recoding is
actually a family of recodings varying with the value of the
divisor. As with multiplier recodings to increase the shift
average, SRT division is most effective in an architecture
which takes advantage of its inherent variable duration.
As with multiplier recodings, the process of quotient
recoding and the resultant freedom to select quotient digits
based upon estimates of the divisor and partial remainders
can be used in implementing higher-radix schemes.6 1 2 I 3
Redundancy in the Partial Remainders Analogous to
multiplication by iterative addition, non-restoring division
is accelerated by decreasing the time to form a partial
remainder. This suggests the use of a limited propagation
adder/subtracter; however, the resulting redundant representation introduces complications. In effect, the redundant representation in the accumulator introduces uncertainties into values of the partial remainders. Since
increasing the redundancy in the quotient tends to decrease
the precision necessary during inspection of the partial
remainder, and since the introduction of redundancy in the
partial remainder requires increased precision during the
inspection, the two methods of employing redundancy tend
to cancel one another. A reasonable compromise may be to
convert the necessary high-order digits of the partial
remainder to a non-redundant form (a propagation
operation) prior to the selection of a quotient digit. This
conversion is considerably less complex than a full
precision, non-redundant addition. This approach is also
exemplified in Reference 6 and analyzed theoretically in
Reference 13.
Evaluating Elementary Functions The efficacy of
redundant representations in accelerating multiplication
and division has led to studies of their use in hardware
evaluation of trigonometric and other elementary functions. Reference 14 is an excellent work in this area.
Redundancy to Provide
Structural Flexibility
Since redundant representations have generally been
limited to the internal registers of the arithmetic unit,
conversion to a non-redundant form is required either
concurrently or as a terminal operation. For this reason
carry-save type structures have not been motivated in the
hope of accelerating the single addition of two operands
since conversion requires a carry propagation. Early studies
in extending the use of redundancy beyond the arithmetic
unit concluded that the cost was too high to be practicable.
Changes in technology, however, suggest a reevaluation of
this conclusion.
The work of Avizienis,1 5Tung,1 6 Pisterzi, ' and others
suggests that another, increasingly important role of
redundant representations is in providing structural
flexibility: modularity, variable operand length, processing
distributed in memory, etc. The emphasis has been on the
use of a so-called signed-digit number system. Signed-digit
arithmetic has been well documented by Avizienis.1 8,1 9
Only the definition and most important properties will be
included in this survey.
Defimition
Signed-digit representations are positional number
representations with a constant integer radix r > 3 in which
the allowed values of the individual digits zi are a sequence
75
of q integers for r + 2 < q < 2r-1, namely (-a, . . .,-1,
0, +1, ..., a). The value of a is chosen from the following
range:
%(ro + 1) < a < ro-1
hre + 1
for odd radices ro > 3;
a < re - 1 for even radices re > 4
Important characteristics of the number system are as
follows:
1. The sign of the algebraic value is the sign of the most
significant non-zero digit.
2. The algebraic value is zero if, and only if, all digits of
signed-digit representation have the value zero.
3. The algebraic sign of a value in signed-digit
representation is formed by changing the sign of the
value of every digit.
4. No carry or borrow need be inserted in the least
significant position of a signed-digit adder, and thus
the structure may be readily partitioned to handle
several operands of shorter length.
Recent suggestions have been made that further
attention should be given to implementing high-speed
decimal arithmetic in view of commercial processing's
increased share of total computation. Those of the
"signed-digit school" have frequently suggested that 4 bits
of a binary code decimal might better be interpreted as the
signed-digit set -6 through +6 and that decimal arithmetic
be conducted redundantly. The author shares the opinion
that this proposal deserves serious evaluation.
Conclusion
A direct quotation from a paper by Avizienis18
succinctly and enthusiastically lists the applications of
signed-digit arithmetic.
The elimination of carry propagation removes a fundamental
constraint of digital arithmetic units and necessitates a
reconsideration of all arithmetic algorithms. The most important
new aspects of signed-digit (to be abbreviated "s-d" from now
on) arithmetic are:
1. the addition time of a parallel adder consisting of any
number of cascaded identical digit-adder packages is
(logically) constant;
2. the most significant digits of the product (as well as of the
quotient) are generated first and may be processed further
before the less significant digits become available;
3. the addition (and subtraction) algorithms apply to
operands of an arbitrary multiple precision (arbitrary
length with respect to the length of the adder): the most
significant sections are added first and may be
immediately processed further;
4. the multiplication and division algorithms are identical
both for single- and multiple-precision operands;
5. in floating-point arithmetic the application of a special
digit value 4( (the space-zero) to designate non-significant
positions allows the implementation of normalized
significant digit arithmetic;
6. the non-significant digit value (space-zero) ( may be
employed to determine the completion of a multipleprecision significant digit algorithm; in this case the
lengths of the operands may be unknown at the beginning
of the algorithm.
A rather novel arithmetic processor may be constructed if
these properties of s-d arithmetic are utilized. The properties (2)
and (3) permit the elimination of temporary storage of
intermediate results in a complex algorithm; right shifts are not
employed, and the flow of operand and result digits is in only
76
one direction (to the left), resembling signal flow through gate
networks. The properties (3), (4) and (6) cancel the distinction
between the implementation of single and multiple-precision
algorithms in an arithmetic processor and allow the completion
of an algorithm to be detected by an inspection of the operands.
Property (5) permits the inclusion of significant digit arithmetic
while retaining all advantages of the number system and without
changing the algorithms. Finally, property (1) permits the
assembly of fixed-time adders of any length from identical
building blocks (without any carry-lookahead or similar logic
structures); this feature promises convenient assembly and
restructuring of arithmetic processors for hardware implementation of complex algorithms in a variable structure computer. The
cost of the various innovations, when compared to a parallel
binary arithmetic unit, is found in the greater complexity of the
individual digit adders and in the increased storage requirements
(for the same precision of operands) due to the redundancy of
the number representation.
A further important consideration in the definition of a
practical signed-digit arithmetic processor is its compatibility
with the widely employed conventional binary number system.
In such an arithmetic the s-d arithmetic processor accepts binary
as well as s-d operands and produces s-d results. Furthermore, a
reconversion algorithm is provided which allows the reconversion
of s-d numbers to conventional binary forms either in the
signed-digit or in a conventional binary arithmetic processor.:
Daniel Atkins is an associate professor of
computer engineering at The University of
Michigan, Ann Arbor, where he is teaching and
conducting research in the area of digital
systems design. He is a member of the Systems
Engineering Laboratory and the program in
Computer, Information, and Control Engineer_ _>
ing (CICE). Dr. Atkins participated in the
design of Iliac III and has also been a member
of the faculty at Bucknell University and the
University of Maryland. He is active in the Computer Society's
Technical Committee on Computer Architecture and served as
program chairman for the Second Symposium on Computer
Arithmetic. He is also active in SIGMICRO, SIGARCH, and
SIGCSE.
Dr. Atkins received the BS degree in electrical engineering from
Bucknell University in 1965, the MS in electrical engineering and
PhD in computer science from the University of Illinois, Urbana, in
1967 and 1970, respectively.
References
1. D. W. Matula, "Radix Arithmetic: Digital Algorithms for
Computer Architecture," Chapter 9 in Applied Computation
Theory, edited by R. Yeh, Prentice-Hall, 1975.
2. Chin Tung, "Arithmetic," Chapter 3 in Computer Science,
edited by Alfonso F. Cardenas, Leon Presser, and Miguel A
Marin, Wiley, 1972.
3. J. E. Robertson, "A Deterministic Process for the Design of
Limited Carry-Borrow Propagation Adders," Report 275,
Department of Computer Science, University of Illinois,
Urbana, July 1967.
4.
R A. Rohatsch, "A Study of Transformations Applicable to
the Development of Limited Carry-Borrow Propagation
Adders," (Ph.D. Thesis), Report 226, Department of Computer
Science, University of Illinois, Urbana, June 1967.
5. R T. Borevec, "The Logical Design of a Class of Limited
Carry-Borrow Propagation Adders," Report No. 275, Department of Computer Science, University of Illinois, Urbana,
August 1968.
6. D. E. Atkins, "Design of the Arithmetic Units of Illiac III: Use
of Redundancy and Higher Radix Methods," IEEE Transactions on Computers, Vol. C-19, No. 8 (August 1969), pp.
720-733.
COMPUTER
7. J. 0. Penhollow, "A Study of Arithmetic Recoding with Applications to
Multiplication and Division," Report
No. 128, Department of Computer
Science, University of Illinois, Urbana,
September 1962.
CALENDAR
Continued from page 7
8. G. W. Reitziesner, "Binary Arithmetic," in Advances in Computers, Vol. 1,
F. L. Alt, ed., Academic Press, New
York, 1960.
9.
a
11. J. E. Robertson, "The Correspondence
between Methods of Digital Division
and Multiplier Recoding Procedures,"
Report No. 252, Department of
Computer Science, University of Illinois, Urbana, December 1967.
12. D. E. Atkins, "Higher Radix Division
Using Estimates of the Divisor and
Partial Remainders," IEEE Transactions on Computers, Vol. C-17, No.
10 (October 1968), pp. 925-934.
13. D. E. Atkins, "A Study of Methods for
Selection of Quotient Digits during
Digital Division," (Ph.D. Thesis), Report No. 397, Department of Computer Science, University of Illinois,
Urbana, June 1970.
14. B. G. DeLugish, "A Class of Algorithms
for Automatic Evaluation of Certain
Elementary Functions in a Binary
Computer," (Ph.D. Thesis), Report No.
399, Department of Computer Science,
University of Illinois, Urbana.
15. A. Avizienis, "On a Flexible Implementation of Digital Computer Arithmetic," Proceedings of IFIP Congress '62,
Munich, 1962, pp. 664-668.
16. C. Tung, "A Combinational Arithmetic
Function Generation System," (Ph.D.
Thesis), Report No. 68-29, Department
of Engineering, UCLA, June 1968.
17. M. J. Pisterzi, "A Limited Connection
Arithmetic Unit," Report No. 398,
Department of Computer Science,
University of Illinois, Urbana, June
1970.
Avizienis, "Binary-Compatible
Signed-Digit Arithmetic," AFIPS Conference Proceedings, Vol. 26, Part 1,
(1964 FJCC), pp. 663-672.
18. A.
19.
Communications and Networks; Interactive Systems and CAD, September
23-25, Uxbridge, England. For information
on these conferences, held concurrently,
contact ONLINE, Brunel University, Uxbridge, Middlesex, England.
C. S. Wallace, "A Suggestion for
Fast-Multiplier," IEEE Transactions on
Electronic Computers, Vol. EC-13,
(February 1964), pp. 14-17.
10. J. E. Robertson, "A New Class of
Digital Division Methods," IRE Transactions on Electronic Computers, Vol.
EC-7 (September 1958), pp. 218-222.
, "Signed-Digit Number Representations for Fast Parallel Arithmetic," IRE Transactions on Electronic
Computers, Vol. 10 (1961), pp.
389-400.
June 1975
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San Francisco, California. Papers and
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Forecasting and Assessment: 1975-2000
are planned. Contact L.S. Coles, Artificial
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7th IFIP Conference, September 8-14,
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c Compcon 75 Fall, September 9-11,
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Symposium on Sparse Matrix Computations, September 9-11, Argonne,
Illinois. For information write James Pool,
Applied Mathematics Division, Argonne
National Laboratory, Argonne, 11 60439.
First National Conference on Software Engineering, Septemberl-12,
Washington, D.C. Immediately follows
Compcon 75 Fall at Washington's Mayflower Hotel. Contact Software Engineering, PO Box 639, Silver Spring, MD 20901.
International Conference on Environmental Sensing and Assessment, September 14-19, Las Vegas, Nevada. Contact IEEE-TAB, 345 E. 47th St., New York,
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Workshop on Data Bases for Interactive
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Wescon 75, September 16-19, San Francisco, California. Contact Alan Mitchell,
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*
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Research, PO Box 3511, Station C, Ottawa,
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1975 IEEE International Symposium on
Electromagnetic Compatibility, October
7-9, San Antonio, Texas. The theme of this
conference, "EMC-The Old and the New,"
depicts the broad range of this technical
program: For further information contact Gus
Van Steenberg, Southwest Research Institute, PO Drawer 28510, San Antonio,
TX 78284.
g Workshop on Methods of Verification
in Design Automation, October 8-10,
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planned on architecture and logic verification, microprogramming, implementation
verification, manufacturing verification, and
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IBM T.J. Watson Research Center, PO Box
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10th National Data Processing Conference, October 13-14, Jerusalem, Israel.
Contact the Program Committee, 10th
National Data Processing Conference, c/o
Kenes Ltd., PO Box 16271, Tel Aviv,
Israel.
Continued on page 79
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