Chapter 16: Design for Testability
Chapter 16: Design for Testability
Prof. Ming-Bo Lin
Department of Electronic Engineering
National Taiwan University of Science and Technology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
Boundary-scan standard
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Chapter 16: Design for Testability
Objectives
After completing this chapter, you will be able to:
™ Describe various fault models
™ Understand the fundamentals of fault detection
™ Understand the difficulties of sequential circuit tests
™ Understand the basic principles of test vector
generation
™ Describe the basic principles of testable circuit
design
™ Understand the principle of boundary scan standard
(IEEE1149.1)
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Chapter 16: Design for Testability
Syllabus
™ Objectives
™ Fault Detection
ƒ Fault models
ƒ Fault detection
ƒ Difficulty of sequential circuit test
™ Test vector generation
™ Testable circuit design
™ Boundary-scan standard
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Chapter 16: Design for Testability
Terminology Definition
™ What is a defect?
™ What is an error?
™ What is a fault?
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Chapter 16: Design for Testability
Fault Models
™ Stuck-at-0 fault
™ Stuck-at-1 fault
™ Bridge fault
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Chapter 16: Design for Testability
Fault Models
™ Stuck-open fault
™ Stuck-closed (stuck-on) fault
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Chapter 16: Design for Testability
Fault Models
™ Fault equivalence
™ Fault collapse
™ Fault coverage
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Chapter 16: Design for Testability
Fault Detection
™ Controllability
™ Observability
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Chapter 16: Design for Testability
Fault Detection
™ A testable fault
™ An untestable fault
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Chapter 16: Design for Testability
Fault Detection
™ An example of complete test set
™ Test vectors are {(0,1), (1,0), (1,1)}
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Chapter 16: Design for Testability
Difficulty of Sequential Circuit Test
™ A homing sequence
™ A preset homing sequence
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Chapter 16: Design for Testability
Difficulty of Sequential Circuit Test
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Chapter 16: Design for Testability
Difficulty of Sequential Circuit Test
™ A transfer sequence
™ A circuit is strongly connected
™ So what are the difficulties of testing sequential
circuits?
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™ Objectives
™ Fault Detection
™ Test vector generation
ƒ
ƒ
ƒ
ƒ
Fault tables
Fault simulation
Boolean differences
Path sensitization
™ Testable circuit design
™ Boundary-scan standard
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Chapter 16: Design for Testability
Fault Tables
™ Form a fault table
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Chapter 16: Design for Testability
Fault Tables
™ Build a fault detection table
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Chapter 16: Design for Testability
Fault Tables
™ Find a reduced fault table
™ The test vectors are: {(0,0,1), (0,1,0), (1,0,0),
(1,1,0)}.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™ Objectives
™ Fault Detection
™ Test vector generation
ƒ
ƒ
ƒ
ƒ
Fault tables
Fault simulation
Boolean differences
Path sensitization
™ Testable circuit design
™ Boundary-scan standard
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Chapter 16: Design for Testability
Fault Simulation
™ The fault simulation process is repeated until:
ƒ All faults are covered
ƒ At least an acceptable number of faults are covered, or
ƒ Some predefined stopping point is reached
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Chapter 16: Design for Testability
Fault Simulation
™ Types of fault simulation
ƒ The row method
ƒ The column method
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Fault Simulation
™ The row method
™ Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0),
(1,1,0)}.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Fault Simulation
™ The column method
™ Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0),
(1,0,1), (1,1,0)}.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™ Objectives
™ Fault Detection
™ Test vector generation
ƒ
ƒ
ƒ
ƒ
Fault tables
Fault simulation
Boolean differences
Path sensitization
™ Testable circuit design
™ Boundary-scan standard
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Chapter 16: Design for Testability
Boolean Differences
™ Boolean difference (Boolean partial derivative)
df ( X )
= f ( xn−1 ,..., xi +1 ,0, xi −1 ,..., x0 ) ⊕ f ( xn−1 ,..., xi +1 ,1, xi −1 ,..., x0 )
dx
= f i (0) ⊕ f i (1)
ƒ Not an effective way
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Chapter 16: Design for Testability
Boolean Differences
™ Example:
f ( X ) = x1 x 2 + x 3
df ( X )
= (1 ⋅ x2 + x3 ) ⊕ (0 ⋅ x2 + x3 ) = ( x2 + x3 ) ⊕ x3
dx1
= ( x2 + x3 )' x3 + ( x2 + x3 )x'3 = x2 x'3
™ To test stuck-at-0 fault at net xi
df ( X )
xi
=1
dxi
™ To test stuck-at-1 fault at net xi
x'i
df ( X )
=1
dxi
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Chapter 16: Design for Testability
Boolean Differences
f ( X ) = ( x1 + x2 )x'3 + x3 x4
™ Stuck-at-0 fault at net α is
x3
df ( X )
= 1 = x3 [ f 3 (0) + f 3 (1)]
dx3
= x'1 x'2 x3 x4 + x1 x3 x'4 + x2 x3 x'4
™ The test vector set is {(0, 0, 1, 1), (1, f, 1, 0), (f, 1, 1, 0)}.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Boolean Differences
™ Stuck-at-0 fault at net β is
y = x1 + x2
f ( X , y ) = yx'3 + x3 x4
y⋅
df ( X , y )
= y[x3 x4 ⊕ ( x'3 + x3 x4 )] = yx'3
dy
= ( x1 + x2 )x'3 = x1 x'3 + x2 x'3
™ The test vector set is {(1, φ, 0, φ), (φ, 1, 0, φ)}.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™ Objectives
™ Fault Detection
™ Test vector generation
ƒ
ƒ
ƒ
ƒ
Fault tables
Fault simulation
Boolean differences
Path sensitization
™ Testable circuit design
™ Boundary-scan standard
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Basic Operations of Path Sensitization
™ Fault sensitization
™ Fault propagation
™ Line justification (Consistency operation)
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Path Sensitization
™ Sensitized path
™ Unsensitized path
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Path Sensitization
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
ƒ Ad hoc testing
ƒ Scan-path methods
ƒ Built-in self test (BIST)
™ Boundary-scan standard
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Ad hoc Testing
™ Basic principles are to increase
ƒ observability
ƒ controllability
™ Methods
ƒ Providing more control and test points
ƒ Using multiplexers to increase the number of internal
control and test points
ƒ Breaking feedback paths
ƒ Using state registers to reduce the additional of I/O pins
required for testing signals
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Ad hoc Testing
™ An example of exhaustive test
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
ƒ Ad hoc testing
ƒ Scan-path methods
ƒ Built-in self test (BIST)
™ Boundary-scan standard
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Scan-Path Methods
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
ƒ Ad hoc testing
ƒ Scan-path methods
ƒ Built-in self test (BIST)
™ Boundary-scan standard
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
BIST Principles
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Automatic Test Pattern Generation (ATPG)(ALFSR)
™ Pr-sequence generator
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Chapter 16: Design for Testability
Automatic Test Pattern Generation (ATPG)
™ A sample primitive polynomials for n from 1 to 60
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Chapter 16: Design for Testability
Signature Generators
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Chapter 16: Design for Testability
A Signature Application Example
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Chapter 16: Design for Testability
A BIBLO Example
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
Boundary-scan standard
ƒ IEEE 1149.1 Standard
ƒ TAP structure
ƒ Boundary scan cells
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
IEEE 1149.1 --- An Application Example
™ Test the entire board-level module
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
The Structure of IEEE 1149.1
™
™
™
™
™
Test access port (TAP)
Data registers
TDO driver
Instruction register and decoder
TAP controller
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
Boundary-scan standard
ƒ IEEE 1149.1 Standard
ƒ TAP structure
ƒ Boundary scan cells
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
The TAP Structure
™
™
™
™
Test data registers (test DRs)
Instruction register and decoder
TAP controller
TDO driver
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Control Signals of IEEE 1149.1
™ Four control signals
ƒ
ƒ
ƒ
ƒ
TCK (test clock, input)
TDI (test data input, input)
TDO (test data output, output)
TMS (test mode select, input)
™ One optional reset signal
ƒ TRST_n (test reset)
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Control Signals of IEEE 1149.1
™ In the normal mode
ƒ TRST_n and TCK are held low
ƒ TMS is held high
™ To prevent race conditions
ƒ Inputs are sampled on the positive edge of TCK
ƒ Output toggle on the negative edge
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Chapter 16: Design for Testability
The State Machine of IEEE 1149.1
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Instruction and Bypass Registers
™ Instruction register cell
ƒ Shift register
ƒ Instruction register
™ Bypass register structure
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
A TDO Driver
™ TDO Driver
ƒ TMS is sampled at the positive edge of TCK
ƒ TDO is sampled at the negative edge of TCK
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Syllabus
™
™
™
™
™
Objectives
Fault Detection
Test vector generation
Testable circuit design
Boundary-scan standard
ƒ IEEE 1149.1 Standard
ƒ TAP structure
ƒ Boundary scan cells
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley
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Chapter 16: Design for Testability
Boundary Scan Cells
™ Operation modes of boundary scan cells (BSC)
ƒ
ƒ
ƒ
ƒ
Normal mode
Capture mode
Scan mode
Update mode
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Chapter 16: Design for Testability
Boundary Scan Cell
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Chapter 16: Design for Testability
Boundary Scan Cells
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Chapter 16: Design for Testability
A Complete Example
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