EENG211/INFE211
Digital Logic Design
Experiment 6
D-type & JK-type flip-flops
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1
2
Student No
Name Surname
Sign
Objective:


To demonstrate the operations and characteristics of D-type flip-flop and JK-type
flip-flop.
Verify that the flip-flop is a bistable multivibrator (has two stable state).And it has
two complementary output states.
USED ICs:
7475
4-Bit Bistable Latch with Complementary
Outputs
7476
Dual J-K M/S Flip-Flop with Preset and
Clear
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EENG211/INFE211
J
0
0
1
1
Digital Logic Design
Flip-Flop Characteristic Tables
JK Flip-Flop
K
Q(t+1)
0
Q(t) (No change)
D
1
0 (Reset)
0
0
1 (Set)
1
1
Q'(t) (Complement)
D Flip-Flop
Q(t+1)
0 (Reset)
1 (Set)
D Flip-Flop
A1. Construct the circuit shown in the figure 1. Double check your connections before you
perform the experiment. Don’t forget to connect pin 5 to +5V and pin 12 to Ground. Then
apply the logic levels given in table 1 and record your data. The pulser switch A will be
used as LOAD signal, so each time you should apply a load signal before recording your
result.
Table 1
D
Q
Q'
0
1
Q1. What is the function of pulser switch A in the above circuit? _______________________.
A2. Wire the circuit shown in Fig 2. The 7475 IC contains four TTL D type flip-flops. Note that
+5 volts is connected to pin 5 and GND is connected to pin 12. Pulser switch A will be used
as load or strobe signal, which transfers input data into the registers.
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EENG211/INFE211
Digital Logic Design
Q2. Set all the data switches to binary 0, and binary 1 at a time. Depress the A pulser switch
before recording the binary number in the register. ____________, ____________.
A3. In Figure 2, load sixteen binary numbers 0000 through 1111 into the register one at a time
by setting the data switches then actuating the A pulser switch. Verify that the switch inputs
do load after the A button is depressed.
JK Flip-Flop
B1. Connect the circuit shown in Fig. 3. Use date switches for the J, K, S (preset) and C (clear)
inputs. Use pulser switch A for the clock CK input. Connect LED indicators to the output.
Connect +5V to pin 5 and GND to pin 13.
B2. First you will check the asynchronous operation of the JK flip-flop. Set J=K=1 with SW0
and SW1. Apply the levels indicated in Table 2 to the S and C inputs. Note the output states
and record them in Table 2. Repeat this step with J=K=0.
TABLE 2
INPUTS
OUTPUTS (J=K=1)
S
C
0
0
0
1
1
0
1
1
Q
Q’
OUTPUST (J=K=0)
Q
Q’
Q1. Do the JK inputs affect the asynchronous operation? _____________________________
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EENG211/INFE211
Digital Logic Design
B3. Next, verify the synchronous operation of the JK flip-flop. Set the S=C=1. Apply the logic
levels indicated in table 3. Record the normal output at (Q) and the [Q(t+1)] output after
applying a single clock pulse from the A pulser switch.
Table 3
INPUTS
OUTPUTS
K
J
0
0
0
1
1
0
1
1
Q
Q(t+1)
Note: Q(t+1) means the state of the Q output after the application of one clock pulse with the
given input.
Q2. Set the inputs as J=1 and K=1. Toggle the clock (CK) input several times with the logic
switch for each set of inputs. What is the effect on the output? _______________________.
Q3. To reset (Q=0) JK flip-flop, what input should be applied? J=_______, & K=_______.
Q4. The flip-flop toggles or complements each time a 1 to 0 occurs on the CK input with
J=_______, & K= __________.
Q5. What is the change on the output (Q) if input signals of J=0 & K=0 is applied? ___________.
Q6. In asynchronous mode of JK flip-flop, the flip flop is reset when C=_______, & S=_______.
Q7. In asynchronous mode of JK flip-flop, the flip flop is set when C=_______, & S=________.
Fall 2010-2011, EENG 115(EENG 211)/INFE 115(INFE 211) Digital Logic Design I, Lab Report.
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