Lab 2
Part 1: 2’s complement Booth’s Multiplication
– Build a 9-bit two's complement multiplier using Booth’s
algorithm.
Part 2: Equivalence Checking
– Decide whether the function pairs are equivalent or not by
implementing these functions and applying inputs to show the
(in)equality.
– Perform Boolean function transformation and verify your
transformation result in LogicWorks.
2’s Complement Booth’s Multiplication
M0/F
Operation
00
No-op
01
Add
10
Subtract
11
No-op
Basic Idea
• Accumulate a partial sum in multiple steps.
• The rightmost bit of the multiplier and the value of the flip-flop are checked
on every step to determine the operation.
• Shift the partial sum and the multiplier one bit to the right on every step.
 Make the partial sum line up with the multiplicand;
 Always check the rightmost bit of multiplier, no need to check higher bits;
 Lower bits of the partial sum shifted into the multiplier register for storage.
Multiplication Example
10112 * 11012
1011
11010
0000101
001011
00101
0001111
multiplicand
multiplier
(sub 1011)
(add 1011)
(sub 1011)
result
step1:
accumulator
multiplier
F
multiplicand
0000
1101
0
1011
accumulator = accumulator - multiplicand
step2:
0101
1101
0
1011
1
1011
right shift
step3:
0010
1110
accumulator = accumulator + multiplicand
step4:
1101
1110
1
1011
0
1011
right shift
1110
1111
accumulator = accumulator - multiplicand
0011
1111
0
1011
1
1011
1
1011
right shift
0001
1111
right shift
Result: 0001111
0000
1111
Signals left for you
M0/F
Operation
00
No-op
01
Add
10
Subtract
11
No-op
• The most significant bit of the accumulator during a shift
– You need to perform sign extension.
• The A/S signal for the adder/subtractor.
– Add if A/S = 0; subtract if A/S = 1.
– You need to drive this signal according to the value of F.
• The Mult input of the controller
– You need to drive it high if and only if Booth’s algorithm requires
an add/subtract operation.
Multiplier Components
• 9-bit Shift Register:
 When LD is set, the parallel data input is loaded into the shift register;
 When SRight is set, the content of the register is shifted 1-bit right, with
the most significant bit fed by VIin.
• 9-bit Adder:
 Output Q(10:0) = A(10:0)+B(10:0)+CI;
 You should convert it into an adder/subtractor with an input A/S.
 If A/S=0, Q(10:0) = A(10:0)+B(10:0).
 If A/S=1, Q(10:0) = A(10:0)-B(10:0).
• Control Unit:
 Handles the multi-cycle process by telling each device what to do on
every cycle until the entire process is finished.
 Every other device simply does what it’s told on each cycle.
• Your job: add necessary logic & connections.
Equivalence Checking
• For each pair of the functions, decide whether they are
equivalent or not:
 AB + C’D + AC’
vs.
(C’ + A)(A + D)(C’ + D)(A’ + B + D’)
 B’ + AC + A’C’
vs.
(A + B’ + C’)(A’ + B’ + C)
• Implement these functions in LogicWorks and compare
their outputs under the same input combinations.
• For each pair, identify all the input combinations that
make it not equivalent.
Boolean Function Transformation
• Given:
 F1 = A  B  C
 F2 = (A?B+A?B’)C? + (A?B+A?B’)C?
• Find the polarity combination for the literals in F2
that make F1 and F2 equivalent.
• Implement F1 and F2 in LogicWorks to test
equivalence.