Four soft-core processors for embedded
systems
Sven-Ake Andersson, Realtime Embedded - January 08, 2013
Since 2000, the folks at Realtime Embedded have concentrated on helping companies develop
embedded systems used in advanced products. Their four primary focus areas are FPGA, Linux,
virtual hardware, and multicore processing systems. Realtime Embedded is involved in customer and
financed research projects, in house and on site, spanning a wide range of industries.
Many of you may have already read my blog called How to design an FPGA from scratch, which I
started to write 2006 and which Max Maxfield wrote about in EE Times for the first time in 2007.
My latest blog describes the work I have performed at Realtime Embedded over the course of the
past year. In this blog, I investigate four soft-core processors and use the same setup as in my first
blog called “learning by doing.” This means that each soft processor will be implemented in an FPGA
and the whole design process will be documented. Click Here to visit my blog.
Why use soft-core processors?
When designing an embedded system in a FPGA, we will most likely need some form of “controller”
in our system. This controller can be a simple microcontroller or a fully-fledged microprocessor
running the Linux operating system. But before we make this decision, let’s first consider the
various options that are available to us.
One solution is to use an off-the-shelf (OTS) microprocessor mounted on the board and connecting to
the FPGA using a standard bus like AMBA. In fact, this still appears to be the most commonly-used
solution. There are times, however, where an OTS processor-based approach will not meet our
requirements. An example would be an application that requires peripheral functionality that is not
available in a discrete solution, or where board real estate is limited.
Another option is to embed a “hard” processor core on the chip. A hard processor core has dedicated
silicon area on the FPGA. This allows it to operate with a core frequency similar to that of a discrete
microprocessor. Examples of hard processor cores used in FPGAs are the PowerPC used in Virtex4/5 and the ARM Cortex-A9 dual-core MCU used in the new Zynq-7000 All Programmable SoC
from Xilinx.
Unfortunately, a hard processor core does not provide the ability to adjust it to better meet the
needs of the application, nor does it allow for the flexibility of adding a processor to an existing
FPGA design or adding an additional processor to provide more processing capabilities.
A soft-core processor solution is one that is implemented entirely in the logic primitives of an FPGA.
Because of this implementation, the processor will not operate at the same clock frequencies or have
the same performance of a discrete solution. In many embedded applications, however, the high
performance achieved by the previous two processing options is not required, and performance can
be traded for expanded functionality, reduced cost, and flexibility.
All the major FPGA vendors have soft-core processors in their product offerings and there are also a
number of companies and organizations developing soft-core processors that are platform
independent and can be implemented in any FPGA design.
Choosing a soft-core processor
When commencing an FPGA design project that will employ a soft-core processor, it can be hard to
decide which processor to use. To help you with this decision and give you quick start guide, let’s
take a closer look at four soft-core processor to see which one would be most suitable for your
platform. Here are the four candidates we will investigate:
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LEON3
MicroBlaze
Nios II
OpenRISC
Prerequisites
Our system will be built on a standard FPGA development board. We will use the CAE tools that are
suggested by the processor provider and try to use license-free tools as much as possible. When
there are no free tools available, we will use an evaluation license from the FPGA vendor. The
system must be able to run a Linux operating system and a Real Time Operating System (RTOS).
The performance of the processor cores will be measured by using the benchmark program
CoreMark.
CPU core benchmarking
Although it doesn’t reflect how you would use a processor in a real application, sometimes it’s
important to isolate the CPU’s core from the other elements of the processor and focus on one key
element. For example, you might want to have the ability to ignore memory and I/O effects and focus
primarily on the pipeline operation. CoreMark (www.coremark.org) is capable of testing a
processor’s basic pipeline structure; it also provides the ability to test basic read/write operations,
integer operations, and control operations.
Installing Linux
We will use the Linux distribution recommended by the processor vendor. An embedded system that
is going to run Linux must include some specific hardware blocks. In a typical system we find the
following:
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CPU with memory management unit (MMU)
Instruction and data caches
DDR3 memory interface
Debug module
Interrupt controller
Ethernet controller
DIP switches, LEDs and push button interface
SPI flash interface
Timer
UART
Clock generator and system reset logic
The LEON3
The LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8
architecture developed by Aeroflex Gaisler AB in Sweden. The model is highly configurable and
particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the
GNU GPL license, allowing free and unlimited use for research and education.
The LEON project was started by the European Space Agency (ESA) in late 1997 to study and
develop a high-performance processor to be used in European space projects. The objectives for the
project were to provide an open, portable and non-proprietary processor design, capable to meet
future requirements for performance, software compatibility and low system cost.
Pros
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No licenses are required for research and education use.
All RTL source code is available
Fast support
Linux and RTOS can be installed
Cons
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Not all FPGA development boards are supported.
Not in widespread use
Summary
The complete design environment for the LEON3, including all the IP cores, can be downloaded from
the Gaisler Aeroflex webpage (www.gaisler.com). The AMBA-2.0 AHB/APB bus has been selected as
the common on-chip bus due to its market dominance (ARM processors) and because it is well
documented and can be used for free without license restrictions. The LEON3 can be easily
configured using a graphical user interface.
More information
Click Here to check out the entire LEON3-based design process in my blog.
The MicroBlaze
The 32-bit MicroBlaze soft processor core from Xilinx is a classic RISC architecture. It was originally
developed around the end of 2000 and the beginning of 2001, and it was released later that year.
Thereafter, the MicroBlaze has continued to evolve with new functions being added on a regular
basis. For example, the most recent release, version 8.20, is equipped with the new AXI bus
interface (Click Here to read the whole story).
Pros
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Can be used in all Xilinx FPGA families
Lots of configuration options
Uses the AXI standard bus
Cons
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Can be used only in Xilinx FPGAs
EDK needs a license
Source code not available
Xilinx Linux support is very basic (this may change now that they have bought PetaLogix)
Summary
The MicroBlaze soft-core processor is fully integrated in the Xilinx FPGA design environment. It can
easily be configured for many different applications from a simple controller to a fully-fledged Linux
processor. The Xilinx EDK environment makes it very easy to configure the processor and add all the
peripherals needed to build a complete processor system.
More information
Click Here to check out the entire MicroBlaze-based design process in my blog.
The OpenRISC
The OpenRISC project was started in 1999 by a group of Slovenian university students. Their aim
was to create an open source microprocessor architecture specification and implementation. Two
years later, they had produced a complete architectural specification, architectural simulator, and
Verilog HDL implementation and made everything publicly available through their new open
hardware community, OpenCores.
The OpenRISC 1200 (OR2100) is a synthesizable CPU core maintained by the developers at
OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC
architecture. The Verilog RTL description is released under the GNU Lesser General Public License
(LGPL).
Pros
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Everything is open source. RTL source code is available.
The ORPSoC reference platform makes it easy to implement an OpenRISC system
The GNU toolchain is fully supported
A large user community can help solve problems
Cons
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Few FPGA development boards are supported
Complicated debug solutions
The Wishbone bus is somewhat outdated
The OpenCores website is confusing
Many IP blocks are not maintained
Summary
Using the OpenRISC 1200 soft-core processor is a mixed bag. It is hard to find the way through the
OpenCores website and there is no obvious starting point for a newbie. But after finding and
downloading the hardware and software support files, it is rather easy to build a system and install
Linux if choosing the right FPGA development board.
More information
Click Here to check out the entire OpenRISC-based design process in my blog.
The Nios II
The Nios II is a proprietary 32-bit RISC architecture processor core developed by Altera for use in
their FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and
generate a custom Nios II core, tailored for his or her specific application requirements. System
designers can extend the Nios II's basic functionality by adding a predefined memory management
unit and/or defining custom instructions and custom peripherals.
Pros
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Easy-to-use development environment
No license required for building a system when using the Quartus II Web Edition
No extra JTAG programming tool needed
Cons
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Can only be used in Altera FPGAs
Some IP cores have time-limited licenses that will stop working after some time. They will continue
to work as long as the development board is connected to your host computer.
Summary
The Altera Quartus II and Nios II Embedded Design Suite make it very easy to build a NIOS II-based
system and to write application software that will run on this system. The complete Nios II system is
specified in the Qsys tool where the processor is configured and all other system components are
added.
More information
Click Here to check out the entire Nios II-based design process in my blog.
Performance measurements
The CoreMark benchmark C-programs were downloaded and installed for the different processors.
The program suite was compiled using the GCC compiler that was part of the SDK installation. The
results are as follows:
To be totally honest, you should take these values "with a grain of salt," because the processors
cores were implemented on different development boards and different GCC compiler versions were
used.
Conclusion
I hope that this investigation will help you in deciding with soft-core processor to use. If you want to
find out more, I would recommend that to build your own system using a similar setup as described
in this blog. Hands-on experience is worth much more than reading colorful sales brochures. If you
have any questions about my findings or about the blog, please don’t hesitate to contact me at
[email protected]
Good luck!
If you found this article to be interest, visit Microcontroller / MCU Designline where – in addition
to my Max's Cool Beans blogs on all sorts of "stuff" – you will find the latest and greatest design,
technology, product, and news articles with regard to all aspects of designing and using
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Last but certainly not least, make sure you check out all of the discussions and other information
resources at All Programmable Planet. For example, in addition to blogs by yours truly,
microcontroller expert Duane Benson is learning how to use FPGAs to augment (sometimes replace)
the MCUs in his robot (and other) projects.