Department of Electrical and Computer Engineering, University of Saskatchewan
CME 342 (VLSI Circuit Design)
Laboratory 4
- Logical Effort and Delay Analysis
By Mulong Li, 2013
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Department of Electrical and Computer Engineering, University of Saskatchewan
1 Logical Effort of an Inverter
In this part, we will analyze the logical effort and parasitic delay of an inverter. We’ll
start by making a testbench.
1.1 Test bench
a) Open Cadence Library Manager in icfb.
b) Create the following cells (schematic and symbols) assuming the size of 2.2u / 1.1u
inverter as the unit size: 4X inverter, 16X inverter, 64X inverter and 256X inverter (4X
inverter means 4 inverters in parallel). We already have the unit size inverter we made in
Lab1, to easily create a 4X inverter, do the following steps:
In Library Manager, right-click and hold on your unit size inverter, choose “copy…”
Change the Cell name in “To” filed to inverter_4X
Click OK, and you’ll see the new cell with name “inverter_4X” in your library
Open the schematic view of 4X inverter, click on PMOS to edit its properties
In the field “Multiplier”, change to 4, and click OK
Do the same for NMOS
Even through the schematic looks exact the same as before, now it represents 4
inverters in parallel
8) Don't forget to change the label for cell name in symbol view
9) Repeat the step 1-8 to create 16X, 64X and 256X inverters
1)
2)
3)
4)
5)
6)
7)
c) Create a new schematic cell, name it something like “inverter_logiceffort”, and arrange
the cells as in Figure 1.1.
Figure 1.1
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Department of Electrical and Computer Engineering, University of Saskatchewan
d) The first 2 inverters are used for shaping the input signal. The 3rd one is our DUT,
Device Under Test. The 4th inverter is its fanout-of-4 load. And the last one is the load
on load. This structure is often used for measuring FO4 delay.
e) For Vpulse, set Rise time and Fall time to 70ps, Pulse width 50ns, and Period 100ns.
f) To add name to a wire, go to Add -> Wire Name…
g) Check and Save. Always do so whenever you change the schematic, otherwise icfb will
give you an error saying the netlist may be corrupt.
1.2 Simulation
a) Open ADE, set the proper model library (you can also load the state from other cells, so
that you don’t have to add the model library every time).
b) Plot “input” and “output”, set Tran stop time to 1u, and start simulation.
c) Measure the rising and falling propagation delay time (tpdr and tpdf). tpdr should be around
65ps, while tpdf is about 78ps. So an FO4 inverter delay is 71.5ps. Since
, we
have
.
Figure 1.2
1.3 Logical effort
Now that we have delay “d” (average of tpdr and tpdf) and electrical effort “h” (fanout-of-4), in
order to use
to calculate logical effort and parasitic delay, we need another
electrical effort with its corresponding delay.
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a) In the testbench, change all inverters to 16X inverter. This can be done by just editing the
properties of the inverters: change the “Cell Name” to the inverter you need. The
schematic should then look like Figure 1.3.
Figure 1.3
b) Run the simulation again, and check if the delay is reduced. tpdr is now around 33ps and
tpdf is approximately 41ps.
c) According to
, now we have 2 equations:
(1)
(2)
d) Solve the equations, we can get logical effort
and parasitic delay
.
Note: You may have noticed that
from our results. In the textbook, the definition
is only for the purpose of hand estimation. It’s based on the assumption that the
diffusion capacitance (Csb and Cbd) of source and drain diffusion regions is comparable to the
gate capacitance. However, the values of diffusion capacitance and gate capacitance are
dependent on the process, and the simulator uses different SPICE models to estimate the values.
Exercise A:
Use the method above, measure the FO4 delay of a 2-input NAND gate. You can use the
same testbench, just change the cells. Connect all floating NAND gate inputs to vdd.
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2 Sizing for minimum path delay
Exercise B:
Estimate the minimum delay of the path from A to B in Figure 2.1 and choose transistor
sizes to achieve this delay. After calculation, design the schematic and measure A to B
delay.
The 1st inverter has unit size P: 2.2um and N: 1.1um, and its gate present a load of C1 = 1
on the input. The output load is equivalent to C5 = 225 (In your schematic use a 1.2pF
capacitor to represent C5).
Figure 2.1
Report:
1. Exercise A: Schematic of NAND2 testbench and its FO4 delay.
2. Exercise B: Calculation of the transistors sizing and A to B delay.
3. Exercise B: Schematic of Figure 2.1, use a Vpulse as input A (r/f time 70ps, pulse
width 50ns, period 100ns), measure A to B average delay.
4. Justify the difference between calculated delay and simulation result
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