338
becomes 1 for 80 ns, and then X is 0 again.
Y
Z
X
11.2
A latch can be constructed from an OR gate, an AND gate, and an inverter connected as follows:
R
Q
P
H
(a) What restriction must be placed on R and H so that P will always equal Q$
(under steady-state conditions)?
(b) Construct a next-state table and derive the characteristic (next-state) equation for
the latch. Answers to Selected Study Guide Questions and Problems 713
Unit 11
(c) Complete
the following timing diagram for the latch.
UNIT 11 Answers
to Problems
11.1
R
x
H
y
Q
z
0
11.3
10
20
30
50P 60
40
70
80
90 100
This problem illustrates the improper operation that can occur if both inputs to an
11.2
(a) Rare
! 11 and
0 cannot
occurback
at the
S-R latch
and H
are!then
changed
to same
0. Fortime.
Figure 11-6, complete the fol(b)timing chart, assuming that each gate has a propagation delay of exactly 10
lowing
"
! RQ"!
HQ
R HthatQinitially
Q"P ! Q
ns. Assume
1 and
0. Note that when t ! 100 ns, S and R are
both changed
to
0.
Then,
10
ns
later,
both
P and Q will change to 1. Because these
0 0
0
0
0 back
0
1to the gate
0
1’s are fed
inputs, what will happen after another 10 ns?
0
0
1
1
0
1
S
0
1
1
1
0
0
0
1
R
X
X
1
1
1
1
0
1
P
1
1
Q
(c)
0
50
100
150
140
200
t(ns)
R
11.4
Design a gated D latch using only NAND gates and one inverter.
11.5
What change must be made to Figure 11-15(a) to implement a falling-edge-triggered
D flip-flop?
Complete the following timing diagram for the modified flip-flop.
Q
H
P
Clock = G1
D
11.3
G2
S
P
R
P
11.6
Q
Q
A reset-dominant
flip-flop
behaves
like
an S-R flip-flop, except that the input
50
100
150
200
S ! R ! 1 is allowed, and the flip-flop is reset when S ! R ! 1.
(a) Derive the characteristic equation for a reset-dominant flip-flop.
340
Answers to Selected Study Guide Questions and Problems
715
Unit 11
11.9 (a)
(b) Complete the timing diagram for the following circuit. Note that the Ck inputs
on the two flip-flops
are different.
ClrN
Unit 11 Problem Solutions
PreN
340
Unit 11
11.1
11.3
Q′1
Q1
J
ClrN
Q′2
Q2
11.2
See FLD p. 646 for solution. For part (b), also us
the following Karnaugh map. Don’t cares come Ck D1 Clock
Ck D2
from the restriction in part (a).
Q1
(b) Complete the timing diagram for the following circuit. Note that the Ck inputs
Q flip-flops are different.
R
on the two
P and Q will oscillate. See FLD p. 646 for timing Q2
1
0
H Q
chart.
Clock
Z responds to X and to Y after 10 ns;; Y responds to Clock
K
CLR
CLR
ClrN Z after 5 ns. See FLD p. 646 for answer.
ClrN
(b)
11.10 Convert by adding
external
gates:
Q′1
Q1
Q′2
Q2
11.4
See FLD p. 647 for solution.
(a) a D flip-flop
to a J-K flip-flop.
Clock
CLR
CLR
(b) a T flip-flop
toClrN
a D flip-flop.
ClrN
Ck D1
Q1
2
(c) a T flip-flop
toClock
a D flip-flopCk
withDclock
enable.
11.5
See FLD p. 647 for solution.
00
0
X
01
0
X
11
1
1
10
0
1
+ = R+HQ
Q2 latch. Assume Q begins atQ1.
Q1 timing diagram for an S-R
11.11 Complete the following
Clock
Q2
11.6 (a)Convert
11.6 (b) See FLD p. 647 for solution.
+
S
S
11.10
external gates:
S R Qby Qadding
R Q
0
1
(a) 0a 0 D0flip-flop
0R to a J-K flip-flop.
00 0
1
11.10 (a) (b) a T flip-flop to a D flip-flop.
0 0 1 1
11.7
See FLD p. 647 for solution.
(c) a T flip-flop
to
a
D
flip-flop
with
clock enable.
01 1
1
0 1 0 0Q
Q
D
Q
0 1 1 the
0 following timing
11 diagram
0
0 for an S-R latch.
11.11J Complete
Q begins at 1.
11.8Assume
See FLD p. 647 for solution.
1 0 table
0 1similar to Figure
11.12 Using
11-8(b),0confirm that each of these circuits is an
K a truth
10 0
Clk
S-R latch. What
happens
when
S
!
R
! 1Q′for each circuit?
1 0 1 1
S
11.9
See FLD p. 648 for solution.
+
Q = R'Q + S R'
1 1 0 1
R
S 1
1 1 1
Q
00
(b)
(c)
11.10
See FLD p. 648 for solution.
Q
0
1
UNIT
01
10
11
Q
Q′
Q
Q
T
Q
T
Q For every input/state combination with the 11.12
11.11 Using a truth
11.12
table similar to Q′
Figure
11-8(b), confirm that each of these circuits is an
D
D
R
condition SR = 0 holding, each circuit obeys the R circuit?
S-R latch. What happens whenCE
S ! R ! 1 forSeach
next-­state equation Q+ = S + R'Q. When S = R =
S
Q′
Q′
Clk
(a)
(b)Clk
in (a), both outputs are 1, and in (b), the latch hol
R
its state.
S
11.13 An AB latch operates as follows: If A !Q0 and B ! 0, the
00 latch state is Q ! 0; if
0 does
01 not change; and when
either
Q A ! 1 or B ! 1 (but not both), the latch output
Q
12 Study
Guide Answers
1
10
both A ! 1 and B ! 1, the latch state is Q ! 1.
11
Q′91,latch.
1. (a)
! 0, H !the
249;state
G !table
0, H and
! 70;
G ! 118,
H ! 118; G !equation
91, H ! 118;
G!
(a) GConstruct
derive
the characteristic
for this
AB
Q′
HDerive
! 118 a circuitR for the AB latch that has four two-input NAND gates and two
(b)
11.13
S R
2. (b)
Sinverters.
0 is 1 between the rising edges of clocks 10 and 11, and also 1 between the
(c) rising
(a)
edges
of clocks
and
16.there any transitions between(b)input combinations
In your
circuit
of Part14(b),
are
D that might cause unreliable operation? Verify your answer.
11.13 An AB latch operates as follows: If A ! 0 and B ! 0, the latch state is Q ! 0; if
G either A ! 1 or B ! 1 (but not both), the latch output does not change; and when
both A ! 1 and B ! 1, the latch state is Q ! 1.
Q (a) Construct the state table and derive the characteristic equation for this AB latch.
(b) Derive a circuit for the AB latch that has four two-input NAND gates and two
S
inverters.
(c)
In
your circuit of Part (b), are there any transitions between input combinations
R
that might cause unreliable operation? Verify your answer.
78