Baker Ch. 12 Static Logic Gates
Introduction to VLSI
 Chapter 12
– Static Logic Gates
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DC NAND, NOR
Layout
AC, Switching
Complex CMOS Gates
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
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Baker Ch. 12 Static Logic Gates

DC NAND, NOR

Introduction to VLSI
DESCRIPTION
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TRANSCONDUCTANCE RATIO
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MODEL W/INPUTS TIED TOGETHER
ASSUME 2-INPUT
WN, 2LN; 2WP, LP
NAND =W/2L (nmos)  2W/2L (pmos)
NOR =W/L (nmos)  4W/L (pmos)
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
2
Baker Ch. 12 Static Logic Gates

LAYOUT NAND, NOR

Introduction to VLSI
DESCRIPTION
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WHAT IS NON-MINIMUM?
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WHAT IS THE IMPACT?
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POLY-TO-POLY SPACING
EXTRA SERIES DIFF RESISTANCE
EXTRA DIFF CAP
HOW MUCH?
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DEPENDS ON SIMS
WHAT IS THE SPEC TARGET?
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
3
Baker Ch. 12 Static Logic Gates

AC, SWITCHING
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PARALLEL CONNECTIONS
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PMOS
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tPLH ~0.7 RP/N (N COXP + CLOAD)
NMOS
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
Introduction to VLSI
tPHL ~0.7 RN/N (N COXN + CLOAD)
SERIES CONNECTIONS
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tDELAY ~ 0.35 R C N2 (CHPT. 2)
PMOS
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tPLH ~0.35 RP COXP N2 + 0.7 N RP CLOAD
NMOS
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tPHL ~0.35 RN COXN N2 + 0.7 N RN CLOAD
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
4
Baker Ch. 12 Static Logic Gates

MUTLI-INPUT GATES

Introduction to VLSI
DESCRIPTION
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PSEUDO-NMOS
USES PMOS AS A LOAD
MUTLI-INPUT W/O AREA PENALTY
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TRADEOFF IS SLOW RISE TIME
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
5
Baker Ch. 12 Static Logic Gates

COMPLEX CMOS GATES

Introduction to VLSI
DESCRIPTION
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AND-OR-INVERT (AOI)
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INSTEAD LOGIC GATE IMPL
NEED INV SIGNALS AS INPUTS
EXAMPLE, Z=A’ + BC
Z’ = [ A’ + BC ]’ = A(B’ + C’)
Z = [ A(B’ + C’) ] ’ = A’ + BC
OUTPUT CAP, SWITCH NMOS ||
3 PMOS, 2 IN SERIES
3 NMOS, 2 IN SERIES
4 PMOS, 2 IN SERIES
4 NMOS, 2 IN SERIES
=
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
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Baker Ch. 12 Static Logic Gates
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CMOS GATES– XOR

Introduction to VLSI
DESCRIPTION
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Z = (A+B) (A’ + B’)
Z’ = [ (A+B) (A’ + B’) ]’ = A’B’ + AB
Z = [ A’B’ + AB ]’
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
7
Baker Ch. 12 Static Logic Gates
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CMOS GATES– ADDER

Introduction to VLSI
DESCRIPTION
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SUM:
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CARRY:
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Sn = An XOR Bn XOR Cn
Sn =
A’n B’n Cn +
A’n Bn C’n +
An B’n C’n +
An Bn Cn
Cn+1 = An Bn + Cn (An + Bn)
C’n+1 = (A’n + B’n) [ C’n + (A’n B’n) ]
COMBINING SUM AND CARRY:
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Sn = (An + Bn + Cn) Cn+1 + An Bn Cn
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
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