© KLMH VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 1 – Introduction Original Authors: 1 Lienig Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu 1.1 Electronic Design Automation (EDA) 1.2 VLSI Design Flow 1.3 VLSI Design Styles 1.4 Layout Layers and Design Rules 1.5 Physical Design Optimizations 1.6 Algorithms and Complexity 1.7 Graph Theory Terminology 1.8 Common EDA Terminology 2 Lienig © KLMH Chapter 1 – Introduction Electronic Design Automation (EDA) In 1965, Gordon Moore (Fairchild) stated that the number of transistors on an IC would double every year. 10 years later, he revised his statement, asserting that they double every 18 months. Since then, this “rule” has been famously known as Moore’s Law. 3 Lienig Moore’s Law Moore: „Cramming more components onto integrated circuits" Electronics, Vol. 38, No. 8, 1965 © KLMH 1.1 Electronic Design Automation (EDA) © KLMH 1.1 Impact of EDA technologies on overall IC design productivity and IC design cost ITRS 2009 Cost Chart (in2009 Millions of Chart Dollars) ITRS Cost (in Millions of Dollars) 120.0 120.0 120.0 100.0 100.0 100.080.0 80.0 80.060.0 60.0 79.0 79.0 56.479.0 56.4 46.7 46.7 33.646.7 33.6 55.7 55.7 42.5 42.5 31.142.5 31.1 35.2 35.2 46.6 46.6 55.7 40.5 40.5 34.046.6 34.0 40.7 27.2 40.7 29.440.5 27.2 29.4 35.2 29.6 33.6 56.4 29.6 21.4 31.1 34.0 21.4 43.5 40.7 40.020.0 44.9 43.5 20.0 44.9 29.4 39.827.2 36.9 39.8 32.9 32.6 36.9 31.7 29.5 29.6 27.0 26.3 32.9 25.2 32.6 27.0 29.5 23.1 31.7 25.2 20.3 19.4 21.416.9 19.4 26.3 16.9 23.1 15.7 20.3 43.5 15.7 44.9 20.0 0.0 39.8 36.9 0.0 32.9 32.6 31.7 29.5 27.0 25.2 20.3 19.4 26.3 16.9202123.12022 2023 2024 15.7 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 0.0 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 60.040.0 40.0 2010 HW 2011 2012 2013 2014 2015 2016 2017 2019 2020Costs 2021+ ESDA 2022 Tool 2023 2024 Total Engineering Costs + EDA EDA Tool Costs Costs Total2018 SW Engineering Engineering Costs Total HW Engineering Costs + Tool Total SW Costs + ESDA Tool Costs Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs 4 Lienig 2009 Electronic Design Automation (EDA) Circuit and Physical Design Process Advancements 1950 -1965 Manual design only. 1965 -1975 Layout editors, e.g., place and route tools, first developed for printed circuit boards. 1975 -1985 More advanced tools for ICs and PCBs, with more sophisticated algorithms. 1985 -1990 First performance-driven tools and parallel optimization algorithms for layout; better understanding of underlying theory (graph theory, solution complexity, etc.). 1990 -2000 First over-the-cell routing, first 3D and multilayer placement and routing techniques developed. Automated circuit synthesis and routability-oriented design become dominant. Start of parallelizing workloads. Emergence of physical synthesis. 2000 - now Design for Manufacturability (DFM), optical proximity correction (OPC), and other techniques emerge at the design-manufacturing interface. Increased reusability of blocks, including intellectual property (IP) blocks. 5 Lienig Time Period © 2011 Springer Verlag © KLMH 1.1 VLSI Design Flow © KLMH 1.2 System Specification Partitioning Architectural Design Functional Design and Logic Design Chip Planning Circuit Design Placement Physical Design Signal Routing Fabrication Timing Closure Packaging and Testing Chip 6 Lienig DRC LVS ERC Physical Verification and Signoff Clock Tree Synthesis © 2011 Springer Verlag ENTITY test is port a: in bit; end ENTITY test; VLSI Design Styles © KLMH 1.3 Layout editor Menu Bar Toolbar Drawing Tools Layer Palette Locator Cell Browser Mouse Buttons Bar Text Windows 7 Lienig Status Bar © 2011 Springer Layout Windows VLSI Design Styles © KLMH 1.3 Common digital cells IN1 IN2 OR OUT IN1 IN2 INV NAND OUT IN OUT IN1 IN2 NOR OUT IN1 IN2 OUT 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 8 Lienig AND VLSI Design Styles Vdd Contact Metal layer Vdd IN2 OUT IN1 IN1 Poly layer OUT Diffusion layer p-type transistor GND GND n-type transistor OUT 9 Lienig IN1 IN2 IN2 © KLMH 1.3 VLSI Design Styles Vdd Contact Metal layer Vdd IN2 OUT IN1 IN1 Poly layer OUT Diffusion layer p-type transistor GND GND n-type transistor OUT Power (Vdd)-Rail Ground (GND)-Rail 10 Lienig IN1 IN2 IN2 © KLMH 1.3 VLSI Design Styles © KLMH 1.3 Standard cell layout with a feedthrough cell Power Pad Pad Standard cell layout using over-the-cell (OTC routing Standard Cells Ground Pad Power Pad A Pad Standard Cells Ground Pad A VDD VDD GND A’ GND Routing Channel 11 Lienig Feedthrough Cell © 2011 Springer Verlag A’ VLSI Design Styles © KLMH 1.3 Layout with macro cells RAM PLA VDD RAM PLA Routing Regions 12 Lienig Pad GND © 2011 Springer Verlag Standard Cell Block VLSI Design Styles © KLMH 1.3 Field-programmable gate array (FPGA) LB LB Switchbox LB SB LB SB LB LB SB LB LB LB 13 Lienig SB Connection © 2011 Springer Verlag LB Logic Element Layout Layers and Design Rules © KLMH 1.4 Layout layers of an inverter cell with external connections Inverter Cell Vdd Metal2 Contact Metal1 Via polysilicon External Connections 14 Lienig GND © 2011 Springer Verlag p/n diffusion Layout Layers and Design Rules © KLMH 1.4 Size rules, such as minimum width: The dimensions of any component (shape), e.g., length of a boundary edge or area of the shape, cannot be smaller than given minimum values. These values vary across different metal layers. Separation rules, such as minimum separation: Two shapes, either on the same layer or on adjacent layers, must be a minimum (rectilinear or Euclidean diagonal) distance apart. Overlap rules, such as minimum overlap: Two connected shapes on adjacent layers must have a certain amount of overlap due to inaccuracy of mask alignment to previously-made patterns on the wafer. 15 Lienig Categories of design rules Layout Layers and Design Rules © KLMH 1.4 Categories of design rules : smallest meaningful technologydependent unit of length a c Minimum Width: a Minimum Separation: b, c, d e Minimum Overlap: e d 16 Lienig © 2011 Springer Verlag b Physical Design Optimizations © KLMH 1.5 Technology constraints enable fabrication for a specific technology node and are derived from technology restrictions. Examples include minimum layout widths and spacing values between layout shapes. Electrical constraints ensure the desired electrical behavior of the design. Examples include meeting maximum timing constraints for signal delay and staying below maximum coupling capacitances. Geometry (design methodology) constraints are introduced to reduce the overall complexity of the design process. Examples include the use of preferred wiring directions during routing, and the placement of standard cells in rows. 17 Lienig Types of constraints Algorithms and Complexity © KLMH 1.6 Runtime complexity Runtime complexity: the time required by the algorithm to complete as a function of some natural measure of the problem size, allows comparing the scalability of various algorithms Complexity is represented in an asymptotic sense, with respect to the input size n, using big-Oh notation or O(…) Runtime t(n) is order f (n), written as t(n) = O(f (n)) when where k is a real number n t ( n) k f ( n) Example: t(n) = 7n! + n2 + 100, then t(n) = O(n!) because n! is the fastest growing term as n . 18 Lienig lim Algorithms and Complexity © KLMH 1.6 Runtime complexity Example: Exhaustively Enumerating All Placement Possibilities Given: n cells Task: find a single-row placement of n cells with minimum total wirelength by using exhaustive enumeration. Solution: The solution space consists of n! placement options. If generating and evaluating the wirelength of each possible placement solution takes 1 s and n = 20, the total time needed to find an optimal solution would be 77,147 years! A number of physical design problems have best-known algorithm complexities that grow exponentially with n, e.g., O(n!), O(nn), and O(2n). Many of these problems are NP-hard (NP: non-deterministic polynomial time) No known algorithms can ensure, in a time-efficient manner, globally optimal solution 19 Lienig Heuristic algorithms are used to find near-optimal solutions Algorithms and Complexity © KLMH 1.6 Heuristic algorithms Deterministic: All decisions made by the algorithm are repeatable, i.e., not random. One example of a deterministic heuristic is Dijkstra’s shortest path algorithm. Stochastic: Some decisions made by the algorithm are made randomly, e.g., using a pseudo-random number generator. Thus, two independent runs of the algorithm will produce two different solutions with high probability. One example of a stochastic algorithm is simulated annealing. In terms of structure, a heuristic algorithm can be Constructive: The heuristic starts with an initial, incomplete (partial) solution and adds components until a complete solution is obtained. 20 Lienig Iterative: The heuristic starts with a complete solution and repeatedly improves the current solution until a preset termination criterion is reached. Algorithms and Complexity © KLMH 1.6 Heuristic algorithms Problem Instance Constructive Algorithm Initial Solution Iterative Improvement Termination Criterion Met? no yes 21 Lienig Return Best-Seen Solution Graph Theory Terminology © KLMH 1.7 Graph Hypergraph b Multigraph b b a e f c a a d f c c 22 Lienig g © 2011 Springer Verlag d e Graph Theory Terminology © KLMH 1.7 Directed graphs with cycles c Directed acyclic graph c f f a d e g a b b d g e 23 Lienig b © 2011 Springer Verlag a Graph Theory Terminology © KLMH 1.7 Undirected graph with maximum node degree 3 Directed tree a b a f c b d c g e f g h i j k 24 Lienig e © 2011 Springer Verlag d Graph Theory Terminology © KLMH 1.7 Rectilinear minimum spanning tree (RMST) b (2,6) Rectilinear Steiner minimum tree (RSMT) b (2,6) Steiner point a (2,1) 25 Lienig a (2,1) c (6,4) © 2011 Springer Verlag c (6,4) Common EDA Terminology © KLMH 1.8 Netlist b N3 N2 N4 y z N5 c Pin-Oriented Netlist (N1: a, x.IN1, y.IN1) (N2: b, x.IN2, y.IN2) (N3: x.OUT, z.IN1) (N4: y.OUT, z.IN2) (N5: z.OUT, c) Net-Oriented Netlist 26 Lienig N1 x (a: N1) (b: N2) (c: N5) (x: IN1 N1, IN2 N2, OUT N3) (y: IN1 N1, IN2 N2, OUT N4) (z: IN1 N3, IN2 N4, OUT N5) © 2011 Springer a Common EDA Terminology © KLMH 1.8 Connectivity graph b N3 N2 N4 z N5 x c z y b c y 27 Lienig N1 a x © 2011 Springer Verlag a Common EDA Terminology © KLMH 1.8 N1 b x N3 N2 N4 y z N5 c b x y z c a 0 0 1 1 0 0 b 0 0 1 1 0 0 x 1 1 0 2 1 0 y 1 1 2 0 1 0 z 0 0 1 1 0 1 c 0 0 0 0 1 0 28 Lienig a a © 2011 Springer Verlag Connectivity matrix Common EDA Terminology © KLMH 1.8 Distance metric between two points P1 (x1,y1) and P2 (x2,y2) d n x2 x1 y2 y1 n n d E ( P1 , P2 ) ( x2 x1 ) 2 ( y2 y1 ) 2 with n = 2: Euclidean distance d M ( P1 , P2 ) x2 x1 y2 y1 n = 1: Manhattan distance P1 (2,4) dM = 7 dE = 5 P2 (6,1) 29 Lienig dM = 7 © KLMH Summary of Chapter 1 IC production experienced huge growth since the 1960s Exponential decrease in transistor size, cost per transistor, power per transistor, etc IC design is impossible without simplification and automation Row-based standard-cell layout with design rules Traditionally, each step in the VLSI design flow has been automated separately by software (CAD) tools Software tools use sophisticated algorithms Many problems in physical design are NP-hard – solved by heuristic algorithms that find near-optimal solutions Deterministic versus stochastic algorithms Constructive algorithms versus iterative improvement Graph algorithms – deal with circuit connectivity Computational geometry – deal with circuit layout 30 Lienig

© Copyright 2022 Paperzz