WATKINS - Chabot College

Engineering 43
Diodes-2
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
[email protected]
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Learning Goals
 Understand the Basic Physics of
Semiconductor PN Junctions which
form most Diode Devices
 Sketch the IV Characteristics of Typical
PN Junction Diodes
 Use the Graphical LOAD-LINE method
to determine the “Operating Point” of
Nonlinear (includes Diodes) Circuits
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Learning Goals
 Analyze diode-containing VoltageRegulation Circuits
 Use various math models for Diode
operation to solve for Diode-containing
Circuit Voltages and/or Currents
IDEAL and
 Learn The difference
PieceWise-Linear
Models
between LARGE-signal
and SMALL-Signal
Circuit Models
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Diode Models
 LoadLine Analysis
works well when the
ckt connected to a
SINGLE Diode can
be “Thevenized”
 However, for
NONLinear ckts,
such as those
containing multiple
diodes, construction
of the LOAD-Curve
Eqn may be difficult,
or even impossible.
 Many such ckts can
be analyzed by
Idealizing the diode
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Diode Models
I

Consider an Electrical Diode →

We can MODEL the V-I
Behavior of this Device in
Several ways
REAL
Behavior
IDEAL
Model
Engineering-43: Engineering Circuit Analysis
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OFFSET
Model
V
LINEAR
Model
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Diode OFF
 Analyze Ckts containing Ideal Diodes
1. Assume (or Guess) a “state” for each
diode. Ideal Diodes have Two states
1. ON → a SHORT Ckt when Fwd Biased
2. OFF →an OPEN Ckt if Reverse Biased
2. Check the Assumed Opens & Shorts
•
Should have Current thru the SHORTS
•
Should have ∆V across the OPENS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Diode ON
Ideal Model (Ideal Rectifier)
Diode OFF
3. Check to see if guesses for i-flow, ∆V,
and BIAS-State are consistent with
the Ideal-Diode Model
4. If i-flow, ∆V, and bias-V are consistent
with the ideal model, then We’re
DONE.
•
If we arrive at even a SINGLE
Inconsistency, then START OVER at
step-1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Diode ON
Ideal Model (Ideal Rectifier)
Example  Ideal Diode
 Find For Ckt Below find: I d1 & Vo
• Use the
Ideal
Diode
Model
Id 2 
 I d1
A
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
 In this Case
VD1 = VD2 = 0
Id 2 
 I d1
A
 Thus D2 Anode is
connected to GND
 Then Find by Ohm
Id 2
 Assume BOTH
Diodes are ON or
Conducting
Engineering-43: Engineering Circuit Analysis
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
10  0  V

 1 mA
10 k
 Next use KCL at
Node-A (in = out)
I d1  I d 2

0   10 V

9.9 k
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
 Thus I d 1  0.0101 mA
Id 2 
 I d1
A
 Now must Check
that both Diodes are
indeed conducting
 From the analysis
I d 1  10 µA
 Using ID2 = 1 mA
I d1

0   10 V

 1 mA
9.9 k
Engineering-43: Engineering Circuit Analysis
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I d 2  1 mA
 Thus the current
thru both Diodes is
positive which is
consistent with the
assumption 
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
Id 2 
 I d1
A
 Since both Diodes
conduct the Top of
Vo is connected to
GND thru D2 & D1
Engineering-43: Engineering Circuit Analysis
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 Another way to think
about this is that
since VD2 = 0 and
VD1 = 0 (by Short
Assumption) Find
Vo = GND+VD2+VD1
= GND + 0 + 0 = 0
 Thus the Answer
I d1  10 µA
Vo  0 V
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
 Find For Ckt Below find: I d1 & Vo
• Use the
Ideal
Diode
Model
• Note the
different
values on
R1 & R2
Id 2 
 I d1
B
– Swapped
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
 As Before
VD1 = VD2 = 0
Id 2 
 I d1
B
 Again VB shorted to
GND thru D1
 Then Find by Ohm
Id 2
 Again Assume
BOTH Diodes are
ON, or Conducting
Engineering-43: Engineering Circuit Analysis
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
10  0  V

 1.01 mA
9.9 k
 Now use KCL at
Node-B (in = out)
I d1  I d 2

0   10 V

10 k
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
 Thus I d1  0.01 mA
Id 2 
 I d1
B
 Now must Check
that both Diodes are
indeed conducting
 From the analysis
I d 1  10 µA
 Using ID2 = 1.01 mA
I d1

0   10 V

 1.01 mA
10 k
Engineering-43: Engineering Circuit Analysis
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I d 2  1.01 mA
 We find and
INCONSISTENCY
and our Assumption
is WRONG 
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
Id 2 
 I d1
B
 In this Case D1 is
an OPEN → ID1 =0
 Current ID2 must
flow thru BOTH
Resistors
 Then Find by Ohm
 Must Iterate
 Assume

10   10 V
Id 2 
 1.005 mA
10  9.9 k
• D1 → OFF
D2 → ON
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
 By KVL & Ohm
VB  10V  10kΩ 1.005mA
Id 2 
VB  0.05 V   50 mV
 Thus D1 is INDEED
Reverse-Biased,
B
Thus the Ckt
operation is
Consistent with our
 Must Check that D1 is
Assumption 
REVERSE Biased as
it is assumed OFF
 I d1
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example  Ideal Diode
Id 2 
 I d1
B
 D2 is ON → VD2 = 0
D1 is OFF →
Current can only
flow thru D2
 In this case Vo = VB
 By the Previous
Calculation, Find
 Calculate Vo by
noting that:
Engineering-43: Engineering Circuit Analysis
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I d1  0 A
Vo  50 mV
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Offset & Linear Models
 The Offset Model
 The Linear Model
 The model eqn:
vD  RbiD  0.6V
 Better than Ideal,
but no account of
Forward-Slope
Engineering-43: Engineering Circuit Analysis
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 Yet more
accurate, but also
does not account for
Rev-Bias Brk-Down
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Point Slope Line Eqn
• Where
y y2  y1
m

x x2  x1
– (x1, y1) & (x2, y2) are
KNOWN Points
Engineering-43: Engineering Circuit Analysis
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 Example: Find Eqn
for line-segment:
18
(3,17)
16
14
12
y
 When constructing
multipiece-wise
linear models, the
Point-Slope
Equation is
extremely Useful
 y  y1   mx  x1 
10
8
6
4
2
(19,5)
4
6
8
10
12
14
16
x
18
y 5  17
12
m


x 19  3
16
3
m
Bruce Mayer, PE
4
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
20
Point Slope Line Eqn
 Using the 2nd Point
 Multiply by m, move
−5 to other side of =
18
(3,17)
16
14
y
12
10
8
6
4
2
(19,5)
4
6
8
10
12
14
16
18
x
3
 y  5   x  19
4
 Can easily convert
to y = mx+b
Engineering-43: Engineering Circuit Analysis
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20
3
 y  5   x  19
4
3
57
y 5   x 
4
4
3
57
y   x 5
4
4
3
57 20
y  x 
4
4
4
3
77
y  x
4
4
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Slopes on vi Curve
 With Reference to
the Point-Slope eqn
v takes over for x,
and
i takes over for y
 The Slope on a vi
Curve is a
conductance
 If the curve is
NONlinear then the
local conductance
is the first Derivative
mvi ,Op
di
Amps


 Siemens
dv Op
Volt
mvi ,Op 
di
g
dv Op
 Recall the Op-Pt is
I
Amps
mvi 

 S iemens
also the Q-Pt
V
Volt
di
mvi ,Op  mvi ,Q 
g
mvi  G
dv
Engineering-43: Engineering Circuit Analysis
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Q
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Slopes on vi Curve
Linear VI Curve
18
 Finally recall that
conductance &
resistance are
Inverses
1
mvi  G 
R
16
I (amps)
14
22
10
8
 Example: Find the
RESISTANCE of the
device associated
with the VI curve
that follows
Engineering-43: Engineering Circuit Analysis
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6
4
2
4
6
8
10
12
V (volts)
14
16
18

I
17  5Amps
mvi 


19  3Volts
V
12A
3
mvi 
 G  Siemens
16V
4
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
20
Slopes on vi Curve
Linear VI Curve
18
 Since R = 1/G Find
the Device
Resistance as
16
I (amps)
14

V
19  3Volts
R

17  5Amps
I
16V 4
R
 Ohms
12A 3
23
12
10
8
mvi  G 
6
4
2
 For a NONlinear vi
curve the local slope
then: r = 1/g
Engineering-43: Engineering Circuit Analysis
1
 R  1.333 
mvi
4
6
8
1
 0.75 S
R
10
12
V (volts)
14
16
 The 1General
Reln
1
rOp 
rOp 
g

di
dv Op
or alternatively
dv
dv
 rQ 
di Op
di Q
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
18
20
Example PieceWise Linear Model
 Construct a
PieceWise
Linear
Model for
the Zener vi
curve
shown at
Right
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
PieceWise Linear Zener
 Us Pt-Slp eqn with
(0.6V,0mA) for Pt-1
iD  0  100mS vD  0.6V 
OR : iD  100mS  vD  60mA
 Segment- B is easy
 m for Segment A

1
I
100  0 mA
mA 


1.6  0.6V
RA V
1
m A  100 mS 
10
Engineering-43: Engineering Circuit Analysis
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iD  0
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
PieceWise Linear Zener
 Us Pt-Slp eqn with
(−6V,0mA) for Pt-1
iD  0  83.3mS vD   6V
OR : iD  83.3mS  vD  500mA
 m for Segment C
 Thus the PieceWise

1
I
0   100mA
Model for the Zener
mC 


RC
V
 6   7.2V
100mA
1
mC 
 83.33 mS 
1.2V
12
Engineering-43: Engineering Circuit Analysis
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 100mS  vD  60mA if

iD  
0
if
83.3mS  v  500mA if
D

v D  0 .6 V
 6 V  v D  0 .6 V
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
vD  6V
Example PieceWise Linear Model
 Alternatively in
terms of
Resistances
 vD
 10  60mA if

iD  
0
if
 vD
12  500mA if

v D  0 .6 V
 6 V  v D  0 .6 V
vD  6V
 ADVICE:
remember the
Pt-Slope
Line-Eqn
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Half-Wave Rectifier Ckt
 Consider an Sinusoidal V-Source, such
as an AC socket in your house,
supplying power to a Load thru a Diode
Power Input
Engineering-43: Engineering Circuit Analysis
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Load Voltage
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
HalfWave Rectifier
 Note that the Doide
is FWD-Biased
during only the
POSITIVE half-cycle
of the Source
 Using this simple ckt
provides to the load
ONLY positive-V; a
good thing
sometimes
Engineering-43: Engineering Circuit Analysis
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 However, the
positive voltage
comes in nasty
PULSES which are
not well tolerated by
positive-V needing
loads
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Smoothed HalfWave Rectifier
 Adding a Cap to the
Circuit creates a
Smoothing effect
 This produces vL(t)
and iL(t) curves
iC  C  dv L dt 
 In this case the
Diode Conducts
ONLY when vs>vC
and vC=vL
Engineering-43: Engineering Circuit Analysis
30
iD  iC  iL
 Note that iL(t) is
approx. constant
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Smoothed HalfWave Rectifier
 The change in
 From the iL(t) curve on
Voltage across the
the previous slide note:
Cap is called “Ripple”
• Cap Discharges for
Ripple
 Often times the load
has a Ripple “Limit”
from which we
determine Cap size
Engineering-43: Engineering Circuit Analysis
31
Almost the ENTIRE
Cycle time, T (diode Off)
• The Load Current is
approx. constant, IL
 Recall from EARLY in
the Class
Charge  Current  Time
Or, symbolical ly : Q  I  T
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Smoothed HalfWave Rectifier
 Also from Cap
 Note that both these
Physics
equations are
(chp3) Qcap  C  Vcap
Approximate, but
they are still useful
 In the Smoother Ckt
for initial Ckt Design
the Cap charges
during the “Ripple”
portion of the curve
 Equating the Charge
& Discharge “Q’s
find
Charge
Discharge
Qcap  C  Vr  I L  T
Engineering-43: Engineering Circuit Analysis
32
 Solving the
equations for the
Cap Value needed
for a given Vr
I L T
C
Vr
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Smoothed HalfWave Rectifier
 Find the Approximate Average Load
Voltage
VL,hi
VL,lo
VL ,avg
VL,avg  Vm 
Engineering-43: Engineering Circuit Analysis
33
VL,hi  VL,lo
2
Vr
 Vm 
2
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Capacitor-Size Effect
 Any load will discharge the
capacitor. In this case, the
output will depend on how
the RC time constant
compares with the period of
the input signal.
 The plots at right consider
the various cases for the
simple circuit above with a
1kHz, 5V sinusoidal input
  RC
T  1 mS
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Full Wave Rectifier
 The half-wave ckt
will take an ACVoltage and convert
it to DC, but the
rectified signal has
gaps in it.
 The gaps can be
eliminated thru the
use of a Full-Wave
rectifier ckt
Engineering-43: Engineering Circuit Analysis
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 The Diodes are
• Face-to-Face (right)
• Butt-to-Butt (left)
 This
rectified
output has
NO Gaps
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Full Wave Rectifier Operation
D1 Supplies V to Load
D4 Supplies V to Load
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Full Wave Rectifier Smoothing
 The Ripple on the
FULL wave Ckt is
about 50% of that
for the half-wave ckt
 Since the Cap
DIScharges only a
half-period
compared to the
half-wave ckt, the
size of the
“smoothing” cap is
then also halved:
I L T
C
2Vr
Engineering-43: Engineering Circuit Analysis
37
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Small Signal Models
 Often we use NonLinear Circuits to
Amplify, or otherwise modify, non-steady
Signals such as ac-sinusoids that are
small compared to the DC Operating
Point, or Q-Point of the Circuit.
 Over a small v or i range even NonLinear
devices appear linear.
This allows us to
construct a so-called
small signal Linear Model
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Small Signal Analysis
 Small signal Analysis is usually done in
Two Parts:
1. Large-Signal DC Operating Point (Q-Pt)
2. Linearize about the Q-Pt using calculus
 Recall from dy y

Calculus
dx x
 This approximation become more
accrate as ∆y & ∆x become smaller
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Small Signal Analsyis
 Now let y→iD, and x→ vD
 Use a DC power Supply
to set the operating point
on the diode curve as
shown at right
• This could be done using LoadLine methods
 From Calculus
diD dvD  iD vD units of A/V or Siemens
 Next Take derivative about the Q-Pt
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx

Small Signal Analysis
 About Q-Pt
diD
dvD
Q
iD

near Q
vD
 Now if we have a
math model for the
vi curve, and we
inject ON TOP of
VDQ a small signal,
∆vD find
Engineering-43: Engineering Circuit Analysis
41
 di
iD   D
 dvD

vD   g d  vD
Q

 The derivative is the
diode small-signal
Conductance at Q
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Small Signal Analysis
 In the large signal
Case: R = 1/G
 By analogy In the
small signal case:
 r = 1/g
 Also since small
signal analysis is
associated with
small amounts that
change with time…
Engineering-43: Engineering Circuit Analysis
42
 Define the Diode’s
DYNAMIC, smallsignal Conductance
and Resistance
diD
gd 
dvD
Q
1  diD
rd 

g d  dvD

1

dvD
 
diD
Q

Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Q
Small Signal Analysis
 Note
Units for rd
1
 Find rd for a
“Shockley” Diode in
majority FWD-Bias
 Recall the
approximation for iD
 Recall Shockley Eqn
 di
rd   D
 dvD
1

Volt
 Amp 


 

Amp
 Volt 
Q

 di
iD   D
 dvD

vD



v

 D
rd
Q

iD  I s e
 Change Notation for
Small
iD  id
Signal
vD  vd
conditions
Engineering-43: Engineering Circuit Analysis
43
 vD

 nVT



1
 Then the Largesignal Operating
Point at vD = VDQ
I DQ  I s e
 VDQ

 nVT



1  I se
 VDQ

 nVT
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx



Small Signal Analysis
 Taking the
derivative of the
Shockely Eqn
diD
dvD
 ISe
 vD

 nVT



Q
 vD 


 
1
1
nV
 I S e T  

nVT nVT 



 Recall from last sld
I se
 VDQ

 nVT



 I DQ
 Sub this Reln into
the Derivative Eqn
Engineering-43: Engineering Circuit Analysis
44
diD
dvD
 
Q
I DQ
1

I DQ 
nVT
nVT
 di
 Recall rd   D
 dvD


Q

1
 Subbing for diD/dvD
 di
rd   D
 dvD
1
1

I
 DQ 
nVT
 
 
I DQ
 nVT 
Q

Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Notation: Large, Small, Total
 VDQ and IDQ are the LARGE Signal
operating point (Q-Pt) DC quantities
• These are STEADY-STATE values
 vD and iD are the TOTAL and
INSTANTANEQOUS quantities
• These values are not necessarily steadystate. To emphasize this we can write vD(t)
and iD(t)
Engineering-43: Engineering Circuit Analysis
45
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Notation: Large, Small, Total
 vd and id are the SMALL, AC quantities
• These values are not necessarily steadystate. To emphasize this we can write vd(t)
and id(t)
 An
Example
for
Diode
Current
notation
Engineering-43: Engineering Circuit Analysis
46
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Effect of Q-Pt Location
 From
Analysis
id 2, pp
id  vd rd
id 1 pp
and
rd 
nVT
I DQ
vd 1 pp
Engineering-43: Engineering Circuit Analysis
47
vd 2 pp
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
DC Srcs  SHORTS in Small-Signal
 In the small-signal equivalent circuit DC
voltage-sources are represented by
SHORT CIRUITS; since their voltage is
CONSTANT, they exhibit ZERO
INCREMENTAL, or SIGNAL, voltage
 Alternative Statement: Since a DC
Voltage source has an ac component of
current, but NO ac VOLTAGE, the DC
Voltage Source is equivalent to a
SHORT circuit for ac signals
Engineering-43: Engineering Circuit Analysis
48
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Setting Q, Injecting v
 Consider this ckt with AC & DC V-srcs
Sets Q
Sets vd
Engineering-43: Engineering Circuit Analysis
49
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Large and Small Signal Ckts
 Recall from Chps 3
and 5 for Caps:
• OPENS to DC
• SHORTS to fast AC
Z C  1  jC 
 Thus if C1 is LARGE
it COUPLES vin(t)
with the rest of the
ckt
 Similarly, Large C2
couples to the Load
Engineering-43: Engineering Circuit Analysis
50
 To Find the Q-point
DEcouple
vin and vo
to arrive at
the DC
circuit
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Large and Small Signal Ckts
 Finding the Large
signal Model was
easy; the Caps acts
as an OPENS
 The Small Signal Ckt
needs more work
 Thus the Small Signal
• Any DC V-Supply is
ckt for the above
a SHORT to GND
• The Diode is
replaced by rd (or gd)
• The Caps are Shorts
Engineering-43: Engineering Circuit Analysis
51
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Example: Small Signal Gain
 Find the Small
Signal Amplification
(Gain), Av, of the
previous circuit
 Note that RC, rd, and
RL are in Parallel
 Using the Small
Signal Circuit
 And vo(t) appears
across this parallel
combination
1
1
1
1



R p RC Rd RL
 The equivalent ckt

vo t 
Engineering-43: Engineering Circuit Analysis
52
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx

Example: Small Signal Gain
 Thus for this Ckt the
Large, Small, and
small-Equivalent ckts

1
1
1
1



R p RC Rd RL
vo t 

 Then the
Amplification (Gain)
by Voltage Divider
Rp
vo
Av 

vin R  R p
Engineering-43: Engineering Circuit Analysis
53
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
LARGE
Signal
Model
All Done for Today
Small
Signal
BJT Amp
 Common Collector
Amplifier
Engineering-43: Engineering Circuit Analysis
54
SMALL
Signal
Model
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Engineering 43
Appendix
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
[email protected]
Engineering-43: Engineering Circuit Analysis
55
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx

vo t 


vo t 

Engineering-43: Engineering Circuit Analysis
56
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Small Signal Analysis
 In the large signal
Case: R = 1/G
 By analogy In the
small signal case:
 r = 1/g
 Also since small
signal analysis is
associated with
small amounts that
change with time…
Engineering-43: Engineering Circuit Analysis
57
 Define the Diode’s
DYNAMIC
Conductance and
Resistance
diD
gd 
dvD
Q
1  diD
rd 

g d  dvD

1

dvD
 
diD
Q

Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Q
P10.67
 Graph vo vs. vi for vi: −5V to +5V
6
5
4
3
2
1
0
-6
-5
-4
-3
-2
-1
0
1
2
-1
-2
-3
-4
-5
file =XY_Plot_0211.xls
Engineering-43: Engineering Circuit Analysis
58
-6
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
3
4
5
6
Engineering-43: Engineering Circuit Analysis
59
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Engineering-43: Engineering Circuit Analysis
60
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Engineering-43: Engineering Circuit Analysis
61
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx
Engineering-43: Engineering Circuit Analysis
62
Bruce Mayer, PE
[email protected] • ENGR-43_Lec-10b_Diode-2_SmallSignalAnalysis.pptx