ケイデンス設計IP／検証IP ケイデンス IP 製品群はプロセッサからミックスシグナルインタフェースまで SOC チップ全体をカバーしており、次世代WiFi や WiGig 等のモバイル・ワイヤレス分野、クラウドや無線基地局等のネットワーク・インフラ分野、およびイメージングやオーディオ等の家電分野の、各アプリケーション向けに統合された IP ソリューションを提供いたします。  設計 IP 特長・SoC チップ全体をカバーする豊富なラインナップ－メモリ、ストレージ、高速インタフェース－DSP、オーディオ、ベースバンド、画像処理－アナログ、セキュリティ Display ® ・ワールドワイドで幅広い分野で採用実績・アプリケーションに最適化・多様なプロセス、テクノロジに対応・高性能、低消費電力を実現・インテグレーション容易・タイムリーで質の高い技術サポートを提供ケイデンスは、実績ある EDA ツール群、信頼性の高いケイデンス検証 IP を併用することで、お客様のシステムの早期実現を可能にいたします。  設計 IP ポートフォリオ Cadence DIP / VIP Portfolio 2014.05 MIPI MIPI D-PHY M-PHY Interface IP Solutions PHY TSMC IP Protocols Performance Controller PCS 65nm LP Ethernet MAC PCS Converter DSI 10M /100M 10M /100M* ● ● 10M /100M /1G 10M /100M /1G* ● ● 10 /40G 10 /40G ● ● ● ● MIPI SM UniPro SLIMbus® PCI EXPRESS BIF PCIe M-PCIe USB LPe LP 28nm HPL ● 40 /100G ● ● 10 /40G 10 /40G ● ● 40 /100G 40 /100G ● ● XAUI / X AUI20 10 /20G ● ● QSGMII R1.2 5G ● DSI TX 1.5Gbps /lane ● † † † † CSI-2 RX 1.5Gbps /lane ● † † † † CSI-2 TX 1.5Gbps /lane ● † † † † DigRF v4, v1.10 3Gbps /lane ● ‡ ‡ ‡ ‡ UniPro 1.6 3 or 6Gbps /lane ● ‡ ‡ ‡ ‡ Device v1.1 Audio / Data ● Manager v1.1 Audio / Data ● BIF v1.0 open drain, HW master Low-speed interface for battery control ● Gen 1 2.5Gbps ● ● Gen 2 5Gbps ● ● Gen 3 8Gbps ● ● M-PCIe ECN, SL HS-G2/ HS-G3 ● ● M-PCIe ECN, ML HS-G2/ HS-G3 ● USB 2.0 HS/ FS/ LS 480 /12/1.5Mbps ● USB 3.0 SS 5Gbps and legacy ● USB 2.0 FS/ LS 12/1.5Mbps ● USB 2.0 HS/ FS 480 /12Mbps ● USB 3.0 SS 5Gbps and legacy ● USB 2.0 HS/ FS 480 /12Mbps ● Hub ● ● ● ● ● ● ● ● ● ● ● ● ● USB 2.0 HS/ FS/ LS 480 /12/1.5Mbps ● ● HSIC Interface USB 2.0 HSIC 480Mbps ● ● SSIC Interface USB 3.0 SSIC 5/2.5/1.25Gbps ● Cadence DIP / VIP Portfolio 2014.05 HPM 10 /40G OTG Table 1: Interface IP Solutions LP 40 /100G Host Device LPe 10G CSI DigRFS M 55nm 40nm ● ● ● ● ● ● ● * Soft PHY available † – D - PHY ‡ – M- PHY Denali Memory IP Solutions PHY Maximum speed Protocols TSMC c 28nm Controller Soft 40nm LP 16nm GF ST 28nm 28nm G HPM LP FF SLP HPP FDSOI ● DDR1 DDR400 ● ● DDR2 DDR800 ● ● DDR2/ DDR1 DDR800 ● ● DDR3*/ DDR2 DDR800 ● ● DDR1333 ● ● ● ● ● ● ● ● DDR1600 ● ● ● ● ● ● ● ● DDR2133 ● ● ● ● ● DDR1600 ● ● ● ● ● DDR2400 ● ● ● ● ● DDR2667 ● ● ● DDR3200 ● DDR1600 ● ● ● ● ● DDR2400 ● ● ● ● ● DDR2667 ● ● ● DDR3* DDR4 DDR4/ DDR3* ● ● ● ● ● DDR3200 ● LPDDR1 DDR400 ● ● LPDDR2 DDR800 ● ● LPDDR2/ LPDDR1 DDR800 ● ● LPDDR2/ DDR3* DDR800 ● ● LPDDR2 DDR1066 ● ● ● ● ● DDR1333 ● ● ● ● ● DDR1600 ● DDR1333 ● DDR1600 ● DDR1333 ● DDR1600 ● DDR1333 ● DDR1600 ● 200MHz ● LPDDR2/ DDR3* LPDDR3 LPDDR3/ LPDDR2 LPDDR3/ LPDDR2/ DDR3* Wide I /O Table 2: Denali Memory IP S olutions Cadence DIP / VIP Portfolio 2014.05 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● * DDR3 includes DDR3L support Storage IP Solutions PHY IP Performance controller NAND Flash 533MT/s NAND Flash ONFI 4/3/2/1, Toggle 1/2 DLL PHY 800MT/s NAND Flash ClearNAND Controller 200MT/s NAND Flash PHY for FPGA 200MT/s SD/SDIO/eMMC soft NAND Flash Async, ONFI 3.2/2/1, Toggle 1/2 Controller SD 4.0 Host 312MBps ● ● ● ● ● ● ● Compact Flash True IDE Controller 166MBps ● Combo SD/SDIO-3.0 /eMMC 4.41 Host 104MBps ● ● Combo SD 4.0 /eMMC5.0 Host 400MBps ● ● Combo SD 3.0 /eMMC 5.0 PHY 400MBps Flash QSPI Controller ● ● 52MBps Table 3: Storage IP Solutions High-Definition Display I P Solutions PHY TSMC IP Protocols Controller/ solution 40nm PHY MHDP TX 65nm LP LP GP ● ● ● ● HDMI1.4 3Gb /lane ● MHL 2.1 3Gbps ● HDMI1.4 3Gb /lane MHL 2.1 3Gbps DP1.2 HBR , SST MHDP TX 6Gbps /lane ● HDP TX 3Gbps /lane ● MHL TX 3Gbps /lane ● MHDP RX 3Gbps /lane HDP RX 3Gbps /lane MHDP TX MHDP RX SMIC Performance LL ● ● ● ● ● ● ● ● ● MHDP RX Table 4: High-Definition Display IP Solutions Cadence DIP / VIP Portfolio 2014.05 ● ● ● Analog IP Solutions TSMC IP 65nm ADC and DAC AFE LP General AFE ● Wi-Fi AFE ● LTE AFE ● 40nm G LP GF 28nm G HPL HPM ● ● ● Low-speed ADC (<10MS/S) ● High-speed DAC (250MHz to 3.52GHz) ● Medium-speed DAC (20 to 250MHz) ● G ● ● ● ● ● ● ● ● 12b 320M ADC ● 7b 3.52G W iGiG ADC ● ● ● LDO ● POR ● ● ● PLL / DLL ● ● ● USB ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● PCIe3/2/1 PHY ● ● PCIe3/2/1 + SRIS + L1 sub-PHY ● ● PCIe2/3, USB3 ● ● 10GKR, PCIe3, X AUI, CEI-6G ● ● PCIe4, USB3.1, HMC-15G-SR ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● M-PHY (HS-G3) Cadence DIP / VIP Portfolio 2014.05 ● ● ● LP ● ● USB3 PHY 40nm ● ● QSGMII / X AUI / Double X AUI HSIC PHY MIPI ● Voltage Monitoring IP Multi-Protocol Monitor Power / Timing High-speed SerDes 12b 160M ADC Table 5: Analog IP Solutions HK ● ● ● ● D-PHY ● SLP ● 12b 80M ADC M-PHY (HS-G2) ● LP ● Audio USB2 OTG PHY LPe ● Low-speed DAC (<10MHz) Temp Monitoring IP 55nm 40nm 28nm 28nm LPe ● LTE/Advanced LTE AFE Medium-speed ADC (20 to 250MS/S) 65nm LP ● ● ● FF UMC ● TriBand (802.11n /ac/ad) AFE High-speed ADC (250MS/S to 3.52GS/S) 16nm LP SMIC ● ● ● ● ● ● ● Systems and Peripherals I P Solutions compatibility Timer Peripheral Bus IP AMBA Rev. 2.0 PW M Pulse W idth Modulator AMBA Rev. 2.0 W DT Watchdog Timer AMBA Rev. 2.0 RTC Real-Time Clock AMBA Rev. 2.0 TTC Triple Timer Counter AMBA Rev. 2.0 AHBC AMBA Rev. 2.0 AHB2APB Bridge AMBA Rev. 2.0 APIC Advanced Peripheral Interrupt Controller AMBA Rev. 2.0 SMC Static Memory Controller AMBA Rev. 2.0 GPIO General Purpose I /O, provides up to 32 programmable ports AMBA Rev 2.0, I C bus specification version 2.0 (100kHz and 400kHz) I2C Inter-Integrated Circuit Bus, functions as a master or slave in a multi-master, two-wire serial I2C bus AMBA Rev 2.0, I2C bus specification version 2.0 (100kHz and 400kHz) I2C HS 2 Serial Interfaces Description AMBA Rev. 2.0 SPI AMBA Rev. 2.0 UART AMBA Rev. 2.0, Philips Inter-IC Sound Bus Specification (1986, revised in 1996) I2S Arbiter for ARM AMBA AHB interface ARM AMBA AHB to APB Bridge IP Inter-Integrated Circuit Bus, High-Speed version Serial Peripheral Interface Bus Universal Async Receiver Transmitter Configurable single- or multi-channel Inter-IC Sound (I2S) bus interface controller Audio Connectivity 8051 Processor AMBA Rev. 2.0 Compatible with Intel ® MCS® 51 instruction set 8051 Microcontroller Legacy Processor R8051XC2 Unidirectional and self-clocking interface for connecting digital audio equipment Intel 8051-compatible µC, fully configurable Compatible with Intel MCS 51 instruction set T8051 Compatible with Intel MCS 251 instruction set 80251XC Intel 80251-compatible µC, over 12 times faster than the 80C51 from Intel C68000 MC68000-compatible microprocessor Compatible with M68000 instruction set Fully compatible with TMS320C25 Obsolete Parts Replacement S/PDIF TMS320C25 Compatible with Intel 80C86 or 80C186 instruction set C80186 Compatible with i387SX instruction set C387L Tiny 8051-compatible µC, very small gate count TI TMS320C25-compatible Digital Signal Processor Series of high-performance, 16-bit microcontrollers compatible with Intel 80C186EC, Intel 80C186XL, Intel 80C186EA, with extended versions of peripherals Intel i387SX-compatible 80-bit math co-processor Compatible with Z80 instruction set Z80 Zilog Z80-compatible microprocessor Improved Zilog ® Z80-compatible CPU S80 Zilog Z80-compatible microprocessor, speed improved Table 6: Systems and Peripherals IP Solutions Cadence DIP / VIP Portfolio 2014.05  SoC 設計の加速に必要な設計・検証 IP をワンストップで提供コントローラ、PHY 等の設計IP 群に加えて、業界で最も整備されたラインナップを有するケイデンス検証IP を活用いただけます。 40 種類以上のプロトコルと最新のメソドロジに対応する設計検証環境の構築により、お客様のシステム実現を加速します。 Controller IP Processor IP  検証 IP 特徴 PHY IP Verification IP One-stop Solution One-stop Solution ・ワールドワイドで 500 を超えるカスタマ実績・数千を超えるデザインで使用実績・6,000 以上のメモリデバイス、40 以上の汎用プロトコルに対応・多様な設計・検証環境に対応  検証 IP ポートフォリオ設計 IP/ 検証 IP お問合せ先日本ケイデンス・デザイン・システムズ社設計IP 専用アドレス [email protected] 検証IP 専用アドレス [email protected] © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, Cadenceロゴは、Cadence Design System, Inc.の米国およびその他の地域における登録商標です。 PCIe, PCI Expressは、PCI-SIGの米国およびその他の地域における登録商標です。その他記載されている製品名および会社名は各社の商標または登録商標です。本資料は、2014 年 5月現在の情報に基づいております。本内容は予告なく変更になることがあります。 Cadence DIP / VIP Portfolio 2014.05