Category

A Posynomial-Based Lagrangian
Relaxation Tuning Tool for
Combinational Gates and Flip-Flops
Sizing
Presenter: Tsung-Tse Lin
Advisor: Prof. Chung-Ping Chen
Outline
• Background and Motivation
• The Optimal Algorithm for Sizing Cyclic
Sequential Circuits
• Experiment Result
• Conclusion
Previous Work
• Several convex optimization methods have been
proposed for sizing combinational circuits.
• C.C.P. Chen et al. ”Fast and Exact Simultaneous Gate and
Wire Sizing by Lagrangian Relaxation,”, in TCAD 1999
• H. Sathyamurthy et al. formulated the sequential
circuit sizing problem as a nonlinear convex program
using the Elmore delay model.
• ”Speeding up Pipelined Circuits through a Combination of
Gate Sizing and Clock Skew Optimization”, in TCAD 1998
Thesis Motivation
• Circuit tuning for sequential circuits
• Most of the existing circuit tuning algorithms are
only for combinational circuit
• However, most of the VLSI circuits contain flip-flops
and/or latches
• Therefore, circuit tuning for sequential circuits is
crucial
Overall Flow
Cell Library
Interconnect Data
Gate-level Netlist
Posynomial
Fitting
Posynomial Model
Tuning
Tool
Optimized Netlist
Flatten the hierarchical netlist
Flatten Netlist
Hierarchical Netlist
Top
A2
A
A
B
C1
A1
A1
A2
C
RAM
RAM
B
C
C2
C1
C2
Top
Our tool in design flow
Concept
Architectural Specs
Floorplanning,
Placement
RTL coding &
simulation
Routing
No
Yes
No
Logic Synthesis
DRC&LVS
Our Tuning Tool
Post-Layout STA
Pre-Layout STA
Timing Ok?
Timing Ok?
Yes
Tape Out
Posynomial Functions
A function f : R n  R, with f  Rn , defined as
f(x)  cx1a1 x a22    x ann , where c  0 and ai  R is called
a monomial function. A posynomial function is the
sum of monomials.
By changing of variables yi  log xi , we can turn
the posynomial function in to the sum of exponentia ls
of affine functions.
Modelling in Posynomial Form
z
k
n
m 1
j 1
i 1
2
ij
((
c
x
)

b
)
  j i
m
Posyfit : Minimize
a
Subject to c j  0, 1  j  k
k
Minimize
((  c j 0.5 1 j 5 2 j 3 3 j )  12) 2 
a
a
a
j1
k
((  c j 0.7 1 j 2 2 j 1 3 j )  15) 2
a
a
j1
Subject to c j  0, 1  j  k
a
Sequential Circuits Tuning Problem
Formulation
minimize  C    cap
1
C:clock, a: arrival time,
D:delay, Tsetup:setup time
2
jN
j
subject to a6  D3  a3
a4  D2  a2
a3  D2  a2
a5out  D4  a4
a3
3
2
a6
D
SET
a5out
Q
a1out  D3  a3
a2
D
a4
SET
1
4
CLR
5
CLR
a5clk
Q
Q
a1clk
Q
a1out
a5clk  D5  a5out
a1clk  D1  a1out
5
a6  Tsetup
 a5clk  C
1
a2  Tsetup
 a1clk  C
Lagrangian Relaxation
Primal
Problem
minimize
1C   2  cap j
jN
subject to a j  D ji  ai ,
i  FF  j  input (i )
aiclk  Di  aiout ,
i  FF
i
a j  Tsetup
 aiclk  C , i  FF  j  input (i )
Lagrangian
Relaxation
L (a, cap, L, s,  )  1C   2  cap j 
jN
 
iFF jinput( i )

iFF

ci
ji
( a j  D ji  ai ) 
( aiclk  Di  aiout ) 
i

(
a

T
 ji j setup  aiclk  C )
iFF jinput( i )
KKT Condition for the Lagrangian
Function Solution
m
l
i 1
i 1
f ( x)   ui g i ( x)   vi hi ( x)  0
ui g i ( x)  0, i  1,  , m
x2
Unconstrained
minimum
g 2 ( x )
(0,2)
 f (x)
ui  0, i  1,  , m
g 1 ( x )
(x)
Contours of f
By taking  a i L  0, we obtain the
 f (xˆ )
required optimality condition on
the arrival time multiplier s :

ji
jinput(i)


ik
koutput(i)
g 3 ( xˆ )
(xˆ )
( 5 ,0)
g 4 ( xˆ )
x1
Iterative Multiplier Adjustment
to be 1 / N , where N is the number
We iterativel y update * using a
modified sub - gradient method given
of the inputs to the sink node.
as follows :
We start by assigning each  j0
 ji   ji (
ci  ci (
a j  D ji
ai
a j  D ji
aiout
) , i  FF  j  input (i )
) , i  FF  j  input (i )
 j  clk
setup
setup


(
ji
ji
a j  Ti setup
ai  C
) , i  FF
 j  input (i )
 j  clk
Algorithm Summary
ALGOTITHM SEQ_SIZE :
Output : optimal gate sizes and
clock period
1. k : 1
 : arbitray initial vector of
lagrange multiplier s satisfying
KKT condition
2. Solve LRS /  by minimizing L 
using L - BFGS - B
Perform STA
3. new : multiplier after subgradien t
multiplier adjustment
Project new to the nearest
point satisfying KKT
4. k : k  1
5. If difference in PP and LRS/λ is
greater th an stopping criteria, go
to step 2
6. Discretize gate sizes to available
drive strengths
Experiment Results on RDC
Circuits(Run PrimeTime)
Netlist Runtim Gate
Name e
Count
Ice.v
Ieu.v
Alu.v
45.813 3575
s
9m31. 17686
84s
6.31s 377
Iqctl.v 9.90s
393
Original
Timing(
ns)
3.30
After
Timing(
ns)
3.18
Percenta
ge(%)
6.95
6.65
4.5
1.81
1.68
7.7
3.06
2.95
3.7
3.7
Conclusion
• In this thesis, we propose an optimal
Lagrangian relaxation based gate sizing
algorithm for globally sizing industrial library
based designs.
• We use nonlinear convex models for accurately
representing the gate delays and can size both
cyclic and acyclic sequential circuits.
• We can also handle the hierarchy of the
synthesized netlist, and integrate our tuning tool
to the standard design flow seamlessly.
Q&A
• Thank You

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